The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
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openpowerwtf d2901c3177 update 6 months ago
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pd update 6 months ago
sim debug 6 months ago
src fix set_ and xucr0 init 6 months ago
verilog yosys cleanup 6 months ago
.gitignore vvp 7 months ago
readme.md add dev 7 months ago

readme.md

Testing RTL with new environments

  • RTL

    • updated source to remove a bunch of Verilator warnings
    • updated source for compatibility with Icaraus -g2012
    • changed the GPR/FPR macro to remove need for clk4x on FPGA; was ugly and not working with either simulator
  • Verilator

    • can IFETCH some ops in ST and SMT2 mode
    • can't get cocotb to build with Verilator (very long compile times)
  • Icarus (w/cocotb)

    • executing boot code until test call with python A2L2 interface
  • Yosys

    • finishes compile

Next To Do

  • create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper)
  • create simple A2L2-WB RTL for easily connecting to Litex, etc.
  • create Litex core wrapper
  • OpenLane experiments with blackbox arrays and yosys/abc/sta
  • create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and valid table
  • parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.)