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565 lines
19 KiB
Verilog
565 lines
19 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_32x70_2w_1r1w.v
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// *! DESCRIPTION : 32 entry x 70 bit x 2 way array,
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// *! 1 read & 1 write port
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// *!
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_32x70_2w_1r1w(
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gnd,
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vdd,
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vcs,
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nclk,
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rd_act,
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wr_act,
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sg_0,
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abst_sl_thold_0,
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ary_nsl_thold_0,
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time_sl_thold_0,
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repr_sl_thold_0,
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func_sl_force,
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func_sl_thold_0_b,
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g8t_clkoff_dc_b,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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g8t_d_mode_dc,
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g8t_mpw1_dc_b,
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g8t_mpw2_dc_b,
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g8t_delay_lclkr_dc,
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d_mode_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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delay_lclkr_dc,
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wr_abst_act,
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rd0_abst_act,
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abist_di,
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abist_bw_odd,
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abist_bw_even,
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abist_wr_adr,
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abist_rd0_adr,
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tc_lbist_ary_wrt_thru_dc,
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abist_ena_1,
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abist_g8t_rd0_comp_ena,
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abist_raw_dc_b,
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obs0_abist_cmp,
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abst_scan_in,
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time_scan_in,
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repr_scan_in,
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func_scan_in,
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abst_scan_out,
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time_scan_out,
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repr_scan_out,
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func_scan_out,
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lcb_bolt_sl_thold_0,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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wr_way,
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wr_addr,
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data_in,
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rd_addr,
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data_out
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);
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parameter addressable_ports = 32; // number of addressable register in this array
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parameter addressbus_width = 5; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
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parameter port_bitwidth = 70; // bitwidth of ports
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parameter ways = 2; // number of ways
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// POWER PINS
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inout gnd;
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inout vdd;
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inout vcs;
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// CLOCK and CLOCKCONTROL ports
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input [0:`NCLK_WIDTH-1] nclk;
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input [0:1] rd_act;
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input [0:1] wr_act;
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input sg_0;
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input abst_sl_thold_0;
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input ary_nsl_thold_0;
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input time_sl_thold_0;
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input repr_sl_thold_0;
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input func_sl_force;
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input func_sl_thold_0_b;
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input g8t_clkoff_dc_b;
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input ccflush_dc;
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input scan_dis_dc_b;
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input scan_diag_dc;
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input g8t_d_mode_dc;
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input [0:4] g8t_mpw1_dc_b;
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input g8t_mpw2_dc_b;
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input [0:4] g8t_delay_lclkr_dc;
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input d_mode_dc;
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input mpw1_dc_b;
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input mpw2_dc_b;
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input delay_lclkr_dc;
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// ABIST
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input wr_abst_act;
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input rd0_abst_act;
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input [0:3] abist_di;
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input abist_bw_odd;
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input abist_bw_even;
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input [0:addressbus_width-1] abist_wr_adr;
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input [0:addressbus_width-1] abist_rd0_adr;
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input tc_lbist_ary_wrt_thru_dc;
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input abist_ena_1;
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input abist_g8t_rd0_comp_ena;
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input abist_raw_dc_b;
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input [0:3] obs0_abist_cmp;
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// Scan
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input [0:1] abst_scan_in;
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input time_scan_in;
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input repr_scan_in;
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input func_scan_in;
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output [0:1] abst_scan_out;
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output time_scan_out;
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output repr_scan_out;
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output func_scan_out;
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// BOLT-ON
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input lcb_bolt_sl_thold_0;
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input pc_bo_enable_2; // general bolt-on enable
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input pc_bo_reset; // reset
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input pc_bo_unload; // unload sticky bits
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input pc_bo_repair; // execute sticky bit decode
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input pc_bo_shdata; // shift data for timing write and diag loop
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input [0:1] pc_bo_select; // select for mask and hier writes
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output [0:1] bo_pc_failout; // fail/no-fix reg
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output [0:1] bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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// Write Ports
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input [0:ways-1] wr_way;
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input [0:addressbus_width-1] wr_addr;
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input [0:port_bitwidth-1] data_in;
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// Read Ports
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input [0:addressbus_width-1] rd_addr;
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output [0:port_bitwidth*ways-1] data_out;
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// tri_32x70_2w_1r1w
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parameter ramb_base_width = 36;
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parameter ramb_base_addr = 9;
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// Configuration Statement for NCsim
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//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
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parameter rd_act_offset = 0;
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parameter data_out0_offset = rd_act_offset + 2;
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parameter data_out1_offset = data_out0_offset + port_bitwidth - 1;
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parameter scan_right = data_out1_offset + port_bitwidth - 1;
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wire [0:port_bitwidth-1] array_wr_data;
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wire [0:35] ramb_data_in_l;
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wire [0:35] ramb_data_in_r;
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wire [0:35] ramb_data_p0_outA;
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wire [0:35] ramb_data_p0_outB;
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wire [0:35] ramb_data_p0_outC;
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wire [0:35] ramb_data_p0_outD;
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wire [0:35] ramb_data_p1_outA;
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wire [0:35] ramb_data_p1_outB;
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wire [0:35] ramb_data_p1_outC;
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wire [0:35] ramb_data_p1_outD;
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wire [0:ramb_base_addr-1] ramb_addr_rd1;
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wire [0:ramb_base_addr-1] ramb_addr_wr_rd0;
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wire [0:ramb_base_addr-1] rd_addr0;
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wire [0:ramb_base_addr-1] wr_addr1;
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wire write_enable_AB;
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wire write_enable_CD;
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wire tiup;
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wire [0:35] tidn;
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wire [0:1] act;
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wire ary_nsl_thold_0_b;
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wire [0:addressable_ports-1] arrA_bit0_scanout;
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wire [0:addressable_ports-1] arrC_bit0_scanout;
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wire [0:addressable_ports-1] arrA_bit0_d;
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wire [0:addressable_ports-1] arrA_bit0_q;
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wire [0:addressable_ports-1] arrC_bit0_d;
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wire [0:addressable_ports-1] arrC_bit0_q;
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wire [0:addressable_ports-1] arrA_bit0_wen;
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wire [0:addressable_ports-1] arrC_bit0_wen;
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reg arrA_bit0_out_d;
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reg arrC_bit0_out_d;
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wire arrA_bit0_out_q;
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wire arrC_bit0_out_q;
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wire arrA_bit0_out_scanout;
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wire arrC_bit0_out_scanout;
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wire [0:port_bitwidth*ways-1] data_out_d;
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wire [0:port_bitwidth*ways-1] data_out_q;
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wire [0:1] rd_act_d;
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wire [0:1] rd_act_q;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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(* analysis_not_referenced="true" *)
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wire unused;
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assign unused = | {ramb_data_p1_outA[0], ramb_data_p1_outA[35], ramb_data_p1_outB[35], ramb_data_p1_outC[0], ramb_data_p1_outC[35], ramb_data_p1_outD[35],
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ramb_data_p0_outA, ramb_data_p0_outB, ramb_data_p0_outC, ramb_data_p0_outD, gnd, vdd, vcs,
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sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b,
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scan_diag_dc, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd,
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abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b,
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obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload,
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pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc, arrA_bit0_scanout, arrC_bit0_scanout, arrA_bit0_out_scanout, arrC_bit0_out_scanout};
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assign tiup = 1'b1;
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assign tidn = 36'b0;
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assign act = rd_act | wr_act;
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assign rd_act_d = rd_act;
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// Data Generate
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assign array_wr_data = data_in;
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assign ramb_data_in_l = {array_wr_data[0:34], 1'b0};
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assign ramb_data_in_r = {array_wr_data[35:69], 1'b0};
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assign write_enable_AB = wr_act[0] & wr_way[0];
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assign write_enable_CD = wr_act[1] & wr_way[1];
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// Read/Write Port Address Generate
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generate
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begin
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genvar t;
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for (t = 0; t < ramb_base_addr; t = t + 1)
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begin : rambAddrCalc
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if (t < ramb_base_addr - addressbus_width)
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begin
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assign rd_addr0[t] = 1'b0;
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assign wr_addr1[t] = 1'b0;
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end
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if (t >= ramb_base_addr - addressbus_width)
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begin
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assign rd_addr0[t] = rd_addr[t - (ramb_base_addr - addressbus_width)];
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assign wr_addr1[t] = wr_addr[t - (ramb_base_addr - addressbus_width)];
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end
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end
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end
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endgenerate
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// Writing on PortA
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// Reading on PortB
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assign ramb_addr_rd1 = rd_addr0;
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assign ramb_addr_wr_rd0 = wr_addr1;
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assign data_out_d = {arrA_bit0_out_q, ramb_data_p1_outA[1:34], ramb_data_p1_outB[0:34], arrC_bit0_out_q, ramb_data_p1_outC[1:34], ramb_data_p1_outD[0:34]};
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assign data_out = data_out_q;
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generate
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begin : arr_bit0
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genvar i;
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for (i = 0; i <= addressable_ports - 1; i = i + 1)
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begin : arr_bit0
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wire [0:addressbus_width-1] iDummy=i;
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assign arrA_bit0_wen[i] = write_enable_AB & (wr_addr == iDummy);
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assign arrC_bit0_wen[i] = write_enable_CD & (wr_addr == iDummy);
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assign arrA_bit0_d[i] = (arrA_bit0_wen[i] == 1'b1) ? array_wr_data[0] :
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arrA_bit0_q[i];
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assign arrC_bit0_d[i] = (arrC_bit0_wen[i] == 1'b1) ? array_wr_data[0] :
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arrC_bit0_q[i];
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end
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end
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endgenerate
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always @(*)
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begin: bit0_read_proc
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reg rd_arrA_bit0;
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reg rd_arrC_bit0;
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//(* analysis_not_referenced="true" *)
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reg [0:31] i;
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rd_arrA_bit0 = 1'b0;
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rd_arrC_bit0 = 1'b0;
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for (i = 0; i <= addressable_ports - 1; i = i + 1)
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begin
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rd_arrA_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrA_bit0_q[i]) | rd_arrA_bit0;
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rd_arrC_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrC_bit0_q[i]) | rd_arrC_bit0;
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end
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arrA_bit0_out_d = rd_arrA_bit0;
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arrC_bit0_out_d = rd_arrC_bit0;
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end
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assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0;
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tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(write_enable_AB),
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.force_t(tidn[0]),
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.d_mode(tidn[0]),
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.delay_lclkr(tidn[0]),
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.mpw1_b(tidn[0]),
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.mpw2_b(tidn[0]),
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.thold_b(ary_nsl_thold_0_b),
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.sg(tidn[0]),
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.scin({addressable_ports{tidn[0]}}),
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.scout(arrA_bit0_scanout),
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.din(arrA_bit0_d),
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.dout(arrA_bit0_q)
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);
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tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(write_enable_CD),
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.force_t(tidn[0]),
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.d_mode(tidn[0]),
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.delay_lclkr(tidn[0]),
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.mpw1_b(tidn[0]),
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.mpw2_b(tidn[0]),
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.thold_b(ary_nsl_thold_0_b),
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.sg(tidn[0]),
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.scin({addressable_ports{tidn[0]}}),
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.scout(arrC_bit0_scanout),
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.din(arrC_bit0_d),
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.dout(arrC_bit0_q)
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);
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tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.force_t(tidn[0]),
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.d_mode(tidn[0]),
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.delay_lclkr(tidn[0]),
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.mpw1_b(tidn[0]),
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.mpw2_b(tidn[0]),
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.thold_b(ary_nsl_thold_0_b),
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.sg(tidn[0]),
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.scin(tidn[0]),
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.scout(arrA_bit0_out_scanout),
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.din(arrA_bit0_out_d),
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.dout(arrA_bit0_out_q)
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);
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tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.force_t(tidn[0]),
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.d_mode(tidn[0]),
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.delay_lclkr(tidn[0]),
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.mpw1_b(tidn[0]),
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.mpw2_b(tidn[0]),
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.thold_b(ary_nsl_thold_0_b),
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.sg(tidn[0]),
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.scin(tidn[0]),
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.scout(arrC_bit0_out_scanout),
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.din(arrC_bit0_out_d),
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.dout(arrC_bit0_out_q)
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);
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RAMB16_S36_S36
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#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
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arr0_A(
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.DOA(ramb_data_p0_outA[0:31]),
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.DOB(ramb_data_p1_outA[0:31]),
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.DOPA(ramb_data_p0_outA[32:35]),
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.DOPB(ramb_data_p1_outA[32:35]),
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.ADDRA(ramb_addr_wr_rd0),
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.ADDRB(ramb_addr_rd1),
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|
.CLKA(nclk[0]),
|
|
.CLKB(nclk[0]),
|
|
.DIA(ramb_data_in_l[0:31]),
|
|
.DIB(tidn[0:31]),
|
|
.DIPA(ramb_data_in_l[32:35]),
|
|
.DIPB(tidn[32:35]),
|
|
.ENA(act[0]),
|
|
.ENB(act[0]),
|
|
.SSRA(nclk[1]), //sreset
|
|
.SSRB(nclk[1]), //sreset
|
|
.WEA(write_enable_AB),
|
|
.WEB(tidn[0])
|
|
);
|
|
|
|
RAMB16_S36_S36
|
|
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
|
|
arr1_B(
|
|
.DOA(ramb_data_p0_outB[0:31]),
|
|
.DOB(ramb_data_p1_outB[0:31]),
|
|
.DOPA(ramb_data_p0_outB[32:35]),
|
|
.DOPB(ramb_data_p1_outB[32:35]),
|
|
.ADDRA(ramb_addr_wr_rd0),
|
|
.ADDRB(ramb_addr_rd1),
|
|
.CLKA(nclk[0]),
|
|
.CLKB(nclk[0]),
|
|
.DIA(ramb_data_in_r[0:31]),
|
|
.DIB(tidn[0:31]),
|
|
.DIPA(ramb_data_in_r[32:35]),
|
|
.DIPB(tidn[32:35]),
|
|
.ENA(act[0]),
|
|
.ENB(act[0]),
|
|
.SSRA(nclk[1]),
|
|
.SSRB(nclk[1]),
|
|
.WEA(write_enable_AB),
|
|
.WEB(tidn[0])
|
|
);
|
|
|
|
RAMB16_S36_S36
|
|
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
|
|
arr2_C(
|
|
.DOA(ramb_data_p0_outC[0:31]),
|
|
.DOB(ramb_data_p1_outC[0:31]),
|
|
.DOPA(ramb_data_p0_outC[32:35]),
|
|
.DOPB(ramb_data_p1_outC[32:35]),
|
|
.ADDRA(ramb_addr_wr_rd0),
|
|
.ADDRB(ramb_addr_rd1),
|
|
.CLKA(nclk[0]),
|
|
.CLKB(nclk[0]),
|
|
.DIA(ramb_data_in_l[0:31]),
|
|
.DIB(tidn[0:31]),
|
|
.DIPA(ramb_data_in_l[32:35]),
|
|
.DIPB(tidn[32:35]),
|
|
.ENA(act[1]),
|
|
.ENB(act[1]),
|
|
.SSRA(nclk[1]),
|
|
.SSRB(nclk[1]),
|
|
.WEA(write_enable_CD),
|
|
.WEB(tidn[0])
|
|
);
|
|
|
|
RAMB16_S36_S36
|
|
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
|
|
arr3_D(
|
|
.DOA(ramb_data_p0_outD[0:31]),
|
|
.DOB(ramb_data_p1_outD[0:31]),
|
|
.DOPA(ramb_data_p0_outD[32:35]),
|
|
.DOPB(ramb_data_p1_outD[32:35]),
|
|
.ADDRA(ramb_addr_wr_rd0),
|
|
.ADDRB(ramb_addr_rd1),
|
|
.CLKA(nclk[0]),
|
|
.CLKB(nclk[0]),
|
|
.DIA(ramb_data_in_r[0:31]),
|
|
.DIB(tidn[0:31]),
|
|
.DIPA(ramb_data_in_r[32:35]),
|
|
.DIPB(tidn[32:35]),
|
|
.ENA(act[1]),
|
|
.ENB(act[1]),
|
|
.SSRA(nclk[1]),
|
|
.SSRB(nclk[1]),
|
|
.WEA(write_enable_CD),
|
|
.WEB(tidn[0])
|
|
);
|
|
|
|
// ####################################################
|
|
// Registers
|
|
// ####################################################
|
|
|
|
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[rd_act_offset:rd_act_offset + 2 - 1]),
|
|
.scout(sov[rd_act_offset:rd_act_offset + 2 - 1]),
|
|
.din(rd_act_d),
|
|
.dout(rd_act_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rd_act_q[0]),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[data_out0_offset:data_out0_offset + port_bitwidth - 1]),
|
|
.scout(sov[data_out0_offset:data_out0_offset + port_bitwidth - 1]),
|
|
.din(data_out_d[0:port_bitwidth - 1]),
|
|
.dout(data_out_q[0:port_bitwidth - 1])
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rd_act_q[1]),
|
|
.force_t(func_sl_force),
|
|
.d_mode(d_mode_dc),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.scin(siv[data_out1_offset:data_out1_offset + port_bitwidth - 1]),
|
|
.scout(sov[data_out1_offset:data_out1_offset + port_bitwidth - 1]),
|
|
.din(data_out_d[port_bitwidth:2 * port_bitwidth - 1]),
|
|
.dout(data_out_q[port_bitwidth:2 * port_bitwidth - 1])
|
|
);
|
|
|
|
assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
|
|
assign func_scan_out = sov[0];
|
|
|
|
assign abst_scan_out = tidn[0:1];
|
|
assign time_scan_out = tidn[0];
|
|
assign repr_scan_out = tidn[0];
|
|
assign bo_pc_failout = tidn[0:1];
|
|
assign bo_pc_diagloop = tidn[0:1];
|
|
endmodule
|