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67 lines
2.3 KiB
Verilog
67 lines
2.3 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILE NAME : tri_fu_mul_bthdcd.vhdl
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// *! DESCRIPTION : Booth Decode
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_fu_mul_bthmux(
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x,
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sneg,
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sx,
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sx2,
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right,
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left,
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q
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);
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input x;
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input sneg; // do not flip the input (add)
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input sx; // shift by 1
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input sx2; // shift by 2
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input right; // bit from the right (lsb)
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output left; // bit from the left
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output q; // final output
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wire center;
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wire q_b;
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assign center = x ^ sneg;
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assign left = center; //output-- rename, no gate
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assign q_b = (~((sx & center) | (sx2 & right)));
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assign q = (~q_b); // output--
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endmodule
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