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344 lines
11 KiB
Verilog
344 lines
11 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 fs / 1 fs
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// *!****************************************************************
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// *! FILENAME : tri_iuq_cpl_arr.v
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// *! DESCRIPTION : iuq completion array (fpga model)
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr);
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parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array
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parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports)
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parameter PORT_BITWIDTH = 64; // bitwidth of ports
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parameter LATCHED_READ = 1'b1;
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parameter LATCHED_READ_DATA = 1'b1;
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parameter LATCHED_WRITE = 1'b1;
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// POWER PINS
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(* ground_pin=1 *)
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inout gnd;
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(* power_pin=1 *)
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inout vdd;
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input [0:`NCLK_WIDTH-1] nclk;
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input delay_lclkr_dc;
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input mpw1_dc_b;
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input mpw2_dc_b;
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input force_t;
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input thold_0_b;
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input sg_0;
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input scan_in;
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output scan_out;
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//-------------------------------------------------------------------
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// Functional
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//-------------------------------------------------------------------
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input re0;
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input [0:ADDRESSBUS_WIDTH-1] ra0;
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output [0:PORT_BITWIDTH-1] do0;
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input re1;
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input [0:ADDRESSBUS_WIDTH-1] ra1;
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output [0:PORT_BITWIDTH-1] do1;
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input we0;
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input [0:ADDRESSBUS_WIDTH-1] wa0;
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input [0:PORT_BITWIDTH-1] di0;
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input we1;
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input [0:ADDRESSBUS_WIDTH-1] wa1;
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input [0:PORT_BITWIDTH-1] di1;
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output perr;
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reg re0_q;
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reg we0_q;
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reg [0:ADDRESSBUS_WIDTH-1] ra0_q;
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reg [0:ADDRESSBUS_WIDTH-1] wa0_q;
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reg [0:PORT_BITWIDTH-1] do0_q;
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wire [0:PORT_BITWIDTH-1] do0_d;
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reg [0:PORT_BITWIDTH-1] di0_q;
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reg re1_q;
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reg we1_q;
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reg [0:ADDRESSBUS_WIDTH-1] ra1_q;
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reg [0:ADDRESSBUS_WIDTH-1] wa1_q;
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reg [0:PORT_BITWIDTH-1] do1_q;
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wire [0:PORT_BITWIDTH-1] do1_d;
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reg [0:PORT_BITWIDTH-1] di1_q;
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wire correct_clk;
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wire reset;
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wire reset_hi;
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reg reset_q;
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wire [0:PORT_BITWIDTH-1] dout0; //std
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wire wen0; //std
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wire [0:ADDRESSBUS_WIDTH-1] addr_w0; //std
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wire [0:ADDRESSBUS_WIDTH-1] addr_r0; //std
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wire [0:PORT_BITWIDTH-1] din0; //std
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wire [0:PORT_BITWIDTH-1] dout1; //std
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wire wen1; //std
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wire [0:ADDRESSBUS_WIDTH-1] addr_w1; //std
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wire [0:ADDRESSBUS_WIDTH-1] addr_r1; //std
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wire [0:PORT_BITWIDTH-1] din1; //std
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reg we1_latch_q;
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reg [0:ADDRESSBUS_WIDTH-1] wa1_latch_q;
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reg [0:PORT_BITWIDTH-1] di1_latch_q;
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(* analysis_not_referenced="true" *)
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wire unused_SPO_0;
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(* analysis_not_referenced="true" *)
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wire unused_SPO_1;
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generate
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assign reset = nclk[1];
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assign correct_clk = nclk[0];
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assign reset_hi = reset;
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// Slow Latches (nclk)
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always @(posedge correct_clk or posedge reset)
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begin: slatch
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begin
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if (reset == 1'b1)
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we1_latch_q <= 1'b0;
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else
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begin
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we1_latch_q <= we1_q;
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wa1_latch_q <= wa1_q;
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di1_latch_q <= di1_q;
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end
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end
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end
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// repower latches for resets
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always @(posedge correct_clk)
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begin: rlatch
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reset_q <= reset_hi;
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end
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// need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag
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// when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order
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// bit of wa1
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assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
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assign wen0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q;
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assign din0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q;
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assign addr_r0 = (ra0_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
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assign addr_w1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
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assign wen1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q;
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assign din1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q;
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assign addr_r1 = (ra1_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
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assign perr = 1'b0;
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begin : xhdl0
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genvar i;
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for (i = 0; i <= PORT_BITWIDTH - 1; i = i + 1)
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begin : array_gen0
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RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0(
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.DPO(dout0[i]),
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.SPO(unused_SPO_0),
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.A0(addr_w0[0]),
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.A1(addr_w0[1]),
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.A2(addr_w0[2]),
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.A3(addr_w0[3]),
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.A4(addr_w0[4]),
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.A5(addr_w0[5]),
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//.A(addr_w0),
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.D(din0[i]),
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.DPRA0(addr_r0[0]),
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.DPRA1(addr_r0[1]),
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.DPRA2(addr_r0[2]),
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.DPRA3(addr_r0[3]),
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.DPRA4(addr_r0[4]),
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.DPRA5(addr_r0[5]),
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//.DPRA(addr_r0),
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.WCLK(correct_clk),
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.WE(wen0)
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);
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RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1(
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.DPO(dout1[i]),
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.SPO(unused_SPO_1),
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.A0(addr_w1[0]),
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.A1(addr_w1[1]),
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.A2(addr_w1[2]),
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.A3(addr_w1[3]),
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.A4(addr_w1[4]),
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.A5(addr_w1[5]),
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//.A(addr_w1),
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.D(din1[i]),
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.DPRA0(addr_r1[0]),
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.DPRA1(addr_r1[1]),
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.DPRA2(addr_r1[2]),
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.DPRA3(addr_r1[3]),
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.DPRA4(addr_r1[4]),
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.DPRA5(addr_r1[5]),
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//.DPRA(addr_r1),
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.WCLK(correct_clk),
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.WE(wen1)
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);
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end
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end
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assign do0_d = (ra0_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
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assign do1_d = (ra1_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
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assign do0 = do0_q;
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assign do1 = do1_q;
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if (LATCHED_READ == 1'b0)
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begin : read_latched_false
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always @(*)
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begin
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re0_q <= re0;
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ra0_q <= ra0;
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re1_q <= re1;
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ra1_q <= ra1;
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end
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end
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if (LATCHED_READ == 1'b1)
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begin : read_latched_true
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always @(posedge correct_clk)
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begin: read_latches
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if (correct_clk == 1'b1)
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begin
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if (reset_q == 1'b1)
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begin
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re0_q <= 1'b0;
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ra0_q <= {ADDRESSBUS_WIDTH{1'b0}};
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re1_q <= 1'b0;
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ra1_q <= {ADDRESSBUS_WIDTH{1'b0}};
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end
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else
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begin
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re0_q <= re0;
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ra0_q <= ra0;
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re1_q <= re1;
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ra1_q <= ra1;
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end
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end
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end
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end
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if (LATCHED_WRITE == 1'b0)
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begin : write_latched_false
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always @(*)
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begin
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we0_q <= we0;
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wa0_q <= wa0;
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di0_q <= di0;
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we1_q <= we1;
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wa1_q <= wa1;
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di1_q <= di1;
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end
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end
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if (LATCHED_WRITE == 1'b1)
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begin : write_latched_true
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always @(posedge correct_clk)
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begin: write_latches
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if (correct_clk == 1'b1)
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begin
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if (reset_q == 1'b1)
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begin
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we0_q <= 1'b0;
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wa0_q <= {ADDRESSBUS_WIDTH{1'b0}};
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di0_q <= {PORT_BITWIDTH{1'b0}};
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we1_q <= 1'b0;
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wa1_q <= {ADDRESSBUS_WIDTH{1'b0}};
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di1_q <= {PORT_BITWIDTH{1'b0}};
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end
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else
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begin
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we0_q <= we0;
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wa0_q <= wa0;
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di0_q <= di0;
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we1_q <= we1;
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wa1_q <= wa1;
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di1_q <= di1;
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end
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end
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end
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end
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if (LATCHED_READ_DATA == 1'b0)
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begin : read_data_latched_false
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always @(*)
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begin
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do0_q <= do0_d;
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do1_q <= do1_d;
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end
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end
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if (LATCHED_READ_DATA == 1'b1)
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begin : read_data_latched_true
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always @(posedge correct_clk)
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begin: read_data_latches
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if (correct_clk == 1'b1)
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begin
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if (reset_q == 1'b1)
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begin
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do0_q <= {PORT_BITWIDTH{1'b0}};
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do1_q <= {PORT_BITWIDTH{1'b0}};
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end
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else
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begin
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do0_q <= do0_d;
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do1_q <= do1_d;
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end
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end
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end
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end
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endgenerate
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endmodule
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