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87 lines
3.2 KiB
Verilog
87 lines
3.2 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// Description: Adder Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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// input phase is important
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// (change X (B) by switching xor/xnor )
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module tri_st_add_csmux(
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sum_0,
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sum_1,
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ci_b,
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sum
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);
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input [0:7] sum_0; // after xor
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input [0:7] sum_1;
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input ci_b;
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output [0:7] sum;
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wire [0:7] sum0_b;
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wire [0:7] sum1_b;
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wire int_ci;
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wire int_ci_t;
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wire int_ci_b;
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assign int_ci = (~ci_b);
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assign int_ci_t = (~ci_b);
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assign int_ci_b = (~int_ci_t);
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assign sum0_b[0] = (~(sum_0[0] & int_ci_b));
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assign sum0_b[1] = (~(sum_0[1] & int_ci_b));
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assign sum0_b[2] = (~(sum_0[2] & int_ci_b));
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assign sum0_b[3] = (~(sum_0[3] & int_ci_b));
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assign sum0_b[4] = (~(sum_0[4] & int_ci_b));
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assign sum0_b[5] = (~(sum_0[5] & int_ci_b));
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assign sum0_b[6] = (~(sum_0[6] & int_ci_b));
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assign sum0_b[7] = (~(sum_0[7] & int_ci_b));
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assign sum1_b[0] = (~(sum_1[0] & int_ci));
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assign sum1_b[1] = (~(sum_1[1] & int_ci));
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assign sum1_b[2] = (~(sum_1[2] & int_ci));
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assign sum1_b[3] = (~(sum_1[3] & int_ci));
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assign sum1_b[4] = (~(sum_1[4] & int_ci));
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assign sum1_b[5] = (~(sum_1[5] & int_ci));
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assign sum1_b[6] = (~(sum_1[6] & int_ci));
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assign sum1_b[7] = (~(sum_1[7] & int_ci));
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assign sum[0] = (~(sum0_b[0] & sum1_b[0]));
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assign sum[1] = (~(sum0_b[1] & sum1_b[1]));
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assign sum[2] = (~(sum0_b[2] & sum1_b[2]));
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assign sum[3] = (~(sum0_b[3] & sum1_b[3]));
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assign sum[4] = (~(sum0_b[4] & sum1_b[4]));
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assign sum[5] = (~(sum0_b[5] & sum1_b[5]));
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assign sum[6] = (~(sum0_b[6] & sum1_b[6]));
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assign sum[7] = (~(sum0_b[7] & sum1_b[7]));
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endmodule
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