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82 lines
2.7 KiB
Verilog
82 lines
2.7 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// Description: Adder Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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// input phase is important
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// (change X (B) by switching xor/xnor )
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module tri_st_add_glbloc(
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g01,
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t01,
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g08,
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t08
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);
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input [0:7] g01; // after xor
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input [0:7] t01;
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output g08;
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output t08;
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wire [0:3] g02_b;
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wire [0:3] t02_b;
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wire [0:1] g04;
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wire [0:1] t04;
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wire g08_b;
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wire t08_b;
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assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1])));
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assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3])));
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assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5])));
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assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7])));
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assign t02_b[0] = (~(t01[0] & t01[1]));
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assign t02_b[1] = (~(t01[2] & t01[3]));
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assign t02_b[2] = (~(t01[4] & t01[5]));
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assign t02_b[3] = (~(t01[6] & t01[7]));
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assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1])));
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assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3])));
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assign t04[0] = (~(t02_b[0] | t02_b[1]));
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assign t04[1] = (~(t02_b[2] | t02_b[3]));
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assign g08_b = (~(g04[0] | (t04[0] & g04[1])));
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assign t08_b = (~((t04[0] & t04[1])));
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assign g08 = (~(g08_b)); // output
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assign t08 = (~(t08_b)); // output
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endmodule
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