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19 lines
417 B
Verilog
19 lines
417 B
Verilog
(* blackbox *)
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module RAMB16_S36_S36 #(
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parameter SIM_COLLISION_CHECK = "ALL",
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) (
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input ENA, CLKA, WEA, SSRA,
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input [8:0] ADDRA,
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input [31:0] DIA,
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input [3:0] DIPA,
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output [31:0] DOA,
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output [3:0] DOPA,
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input [8:0] ADDRB,
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input [31:0] DIB,
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input [3:0] DIPB,
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input ENB, CLKB, WEB, SSRB,
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output [31:0] DOB,
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output [3:0] DOPB
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);
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endmodule
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