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85 lines
3.4 KiB
Verilog
85 lines
3.4 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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////############################################################################
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////##### Q Quotient digit selection logic #######
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////############################################################################
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module fu_divsqrt_q_table(
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x,
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cin,
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q
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);
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`include "tri_a2o.vh"
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input [0:3] x;
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input cin;
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output q;
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wire nor123;
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wire nor123_b;
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wire x0_b;
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wire not0and1or2or3_b;
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wire nor01;
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wire nor23;
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wire not0or1or2or3_and_cin_b;
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//// Implements this table:
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// assign exx_q_bit0_prebuf = (exx_sum4 == 4'b0000) ? exx_q_bit0_cin :
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// (exx_sum4 == 4'b0001) ? 1'b1 :
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// (exx_sum4 == 4'b0010) ? 1'b1 :
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// (exx_sum4 == 4'b0011) ? 1'b1 :
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// (exx_sum4 == 4'b0100) ? 1'b1 :
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// (exx_sum4 == 4'b0101) ? 1'b1 :
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// (exx_sum4 == 4'b0110) ? 1'b1 :
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// (exx_sum4 == 4'b0111) ? 1'b1 :
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// 1'b0;
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tri_nor3 #(.WIDTH(1), .BTR("NOR3_X4M_A9TH")) DIVSQRT_N_TABLE_NOR3_01(nor123, x[1], x[2], x[3]);
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tri_inv #(.WIDTH(1), .BTR("INV_X3M_A9TH")) DIVSQRT_N_TABLE_INV_02a(nor123_b, nor123);
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tri_inv #(.WIDTH(1), .BTR("INV_X5B_A9TH")) DIVSQRT_N_TABLE_INV_02b(x0_b, x[0]);
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tri_nand2 #(.WIDTH(1), .BTR("NAND2_X4A_A9TH")) DIVSQRT_N_TABLE_NAND2_03(not0and1or2or3_b, x0_b, nor123_b);
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//
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tri_nor2 #(.WIDTH(1), .BTR("NOR2_X8B_A9TH")) DIVSQRT_N_TABLE_NOR2_01a(nor01, x[0], x[1]);
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tri_nor2 #(.WIDTH(1), .BTR("NOR2_X4B_A9TH")) DIVSQRT_N_TABLE_NOR2_01b(nor23, x[2], x[3]);
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tri_nand3 #(.WIDTH(1), .BTR("NAND3_X6M_A9TH")) DIVSQRT_N_TABLE_NAND3_02(not0or1or2or3_and_cin_b, nor01, nor23, cin);
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//
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tri_nand2 #(.WIDTH(1), .BTR("NAND2_X8A_A9TH")) DIVSQRT_N_TABLE_NAND2_04(q, not0or1or2or3_and_cin_b, not0and1or2or3_b);
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endmodule
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