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152 lines
5.7 KiB
Verilog
152 lines
5.7 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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////############################################################################
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////##### FUQ_GEST_add11.VHDL #########
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////##### side pipe for graphics estimates #########
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////##### flogefp, fexptefp #########
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////##### #########
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////############################################################################
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module fu_gst_add11(
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a_b,
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b_b,
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s0
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);
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`include "tri_a2o.vh"
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input [0:10] a_b; // inverted adder input
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input [0:10] b_b; // inverted adder input
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output [0:10] s0;
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(* NO_MODIFICATION="TRUE" *)
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wire [0:10] p1;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:10] g1;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:9] t1;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:10] g2_b;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:10] g4;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:10] g8_b;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:10] c16;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:8] t2_b;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:6] t4;
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(* NO_MODIFICATION="TRUE" *)
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wire [1:2] t8_b;
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assign p1[0:10] = (a_b[0:10] ^ b_b[0:10]);
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assign g1[1:10] = (~(a_b[1:10] | b_b[1:10]));
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assign t1[1:9] = (~(a_b[1:9] & b_b[1:9]));
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//---------------------------------------------
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// carry chain ---
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//---------------------------------------------
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assign g2_b[1] = (~(g1[1] | (t1[1] & g1[2])));
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assign g2_b[2] = (~(g1[2] | (t1[2] & g1[3])));
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assign g2_b[3] = (~(g1[3] | (t1[3] & g1[4])));
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assign g2_b[4] = (~(g1[4] | (t1[4] & g1[5])));
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assign g2_b[5] = (~(g1[5] | (t1[5] & g1[6])));
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assign g2_b[6] = (~(g1[6] | (t1[6] & g1[7])));
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assign g2_b[7] = (~(g1[7] | (t1[7] & g1[8])));
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assign g2_b[8] = (~(g1[8] | (t1[8] & g1[9])));
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assign g2_b[9] = (~(g1[9] | (t1[9] & g1[10]))); //done
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assign g2_b[10] = (~(g1[10]));
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assign t2_b[1] = (~(t1[1] & t1[2]));
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assign t2_b[2] = (~(t1[2] & t1[3]));
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assign t2_b[3] = (~(t1[3] & t1[4]));
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assign t2_b[4] = (~(t1[4] & t1[5]));
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assign t2_b[5] = (~(t1[5] & t1[6]));
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assign t2_b[6] = (~(t1[6] & t1[7]));
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assign t2_b[7] = (~(t1[7] & t1[8]));
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assign t2_b[8] = (~(t1[8] & t1[9]));
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assign g4[1] = (~(g2_b[1] & (t2_b[1] | g2_b[3])));
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assign g4[2] = (~(g2_b[2] & (t2_b[2] | g2_b[4])));
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assign g4[3] = (~(g2_b[3] & (t2_b[3] | g2_b[5])));
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assign g4[4] = (~(g2_b[4] & (t2_b[4] | g2_b[6])));
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assign g4[5] = (~(g2_b[5] & (t2_b[5] | g2_b[7])));
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assign g4[6] = (~(g2_b[6] & (t2_b[6] | g2_b[8])));
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assign g4[7] = (~(g2_b[7] & (t2_b[7] | g2_b[9]))); //done
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assign g4[8] = (~(g2_b[8] & (t2_b[8] | g2_b[10]))); //done
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assign g4[9] = (~(g2_b[9]));
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assign g4[10] = (~(g2_b[10]));
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assign t4[1] = (~(t2_b[1] | t2_b[3]));
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assign t4[2] = (~(t2_b[2] | t2_b[4]));
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assign t4[3] = (~(t2_b[3] | t2_b[5]));
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assign t4[4] = (~(t2_b[4] | t2_b[6]));
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assign t4[5] = (~(t2_b[5] | t2_b[7]));
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assign t4[6] = (~(t2_b[6] | t2_b[8]));
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assign g8_b[1] = (~(g4[1] | (t4[1] & g4[5])));
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assign g8_b[2] = (~(g4[2] | (t4[2] & g4[6])));
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assign g8_b[3] = (~(g4[3] | (t4[3] & g4[7]))); //done
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assign g8_b[4] = (~(g4[4] | (t4[4] & g4[8]))); //done
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assign g8_b[5] = (~(g4[5] | (t4[5] & g4[9]))); //done
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assign g8_b[6] = (~(g4[6] | (t4[6] & g4[10]))); //done
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assign g8_b[7] = (~(g4[7]));
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assign g8_b[8] = (~(g4[8]));
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assign g8_b[9] = (~(g4[9]));
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assign g8_b[10] = (~(g4[10]));
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assign t8_b[1] = (~(t4[1] & t4[5]));
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assign t8_b[2] = (~(t4[2] & t4[6]));
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assign c16[1] = (~(g8_b[1] & (t8_b[1] | g8_b[9]))); //done
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assign c16[2] = (~(g8_b[2] & (t8_b[2] | g8_b[10]))); //done
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assign c16[3] = (~(g8_b[3]));
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assign c16[4] = (~(g8_b[4]));
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assign c16[5] = (~(g8_b[5]));
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assign c16[6] = (~(g8_b[6]));
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assign c16[7] = (~(g8_b[7]));
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assign c16[8] = (~(g8_b[8]));
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assign c16[9] = (~(g8_b[9]));
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assign c16[10] = (~(g8_b[10]));
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//---------------------------------------------
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// final result ---
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//---------------------------------------------
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assign s0[0:9] = p1[0:9] ^ c16[1:10];
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assign s0[10] = p1[10];
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endmodule
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