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165 lines
6.2 KiB
Verilog
165 lines
6.2 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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////############################################################################
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////##### FUQ_GEST_inc19.VHDL #########
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////##### side pipe for graphics estimates #########
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////##### flogefp, fexptefp #########
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////##### #########
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////############################################################################
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module fu_gst_inc19(
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a,
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o
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);
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`include "tri_a2o.vh"
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input [1:19] a;
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output [1:19] o; // sum if ci=1
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wire [01:19] a_sum;
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wire [02:19] a_cout_b;
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(* NO_MODIFICATION="TRUE" *)
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wire [02:19] g2_b;
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(* NO_MODIFICATION="TRUE" *)
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wire [02:19] g4;
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(* NO_MODIFICATION="TRUE" *)
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wire [02:19] g8_b;
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(* NO_MODIFICATION="TRUE" *)
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wire [02:19] g16;
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assign g2_b[19] = (~(a[19]));
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assign g2_b[18] = (~(a[18] & a[19]));
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assign g2_b[17] = (~(a[17] & a[18]));
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assign g2_b[16] = (~(a[16] & a[17]));
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assign g2_b[15] = (~(a[15] & a[16]));
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assign g2_b[14] = (~(a[14] & a[15]));
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assign g2_b[13] = (~(a[13] & a[14]));
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assign g2_b[12] = (~(a[12] & a[13]));
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assign g2_b[11] = (~(a[11] & a[12]));
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assign g2_b[10] = (~(a[10] & a[11]));
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assign g2_b[9] = (~(a[9] & a[10]));
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assign g2_b[8] = (~(a[8] & a[9]));
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assign g2_b[7] = (~(a[7] & a[8]));
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assign g2_b[6] = (~(a[6] & a[7]));
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assign g2_b[5] = (~(a[5] & a[6]));
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assign g2_b[4] = (~(a[4] & a[5]));
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assign g2_b[3] = (~(a[3] & a[4]));
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assign g2_b[2] = (~(a[2] & a[3]));
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assign g4[19] = (~(g2_b[19]));
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assign g4[18] = (~(g2_b[18]));
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assign g4[17] = (~(g2_b[17] | g2_b[19]));
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assign g4[16] = (~(g2_b[16] | g2_b[18]));
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assign g4[15] = (~(g2_b[15] | g2_b[17]));
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assign g4[14] = (~(g2_b[14] | g2_b[16]));
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assign g4[13] = (~(g2_b[13] | g2_b[15]));
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assign g4[12] = (~(g2_b[12] | g2_b[14]));
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assign g4[11] = (~(g2_b[11] | g2_b[13]));
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assign g4[10] = (~(g2_b[10] | g2_b[12]));
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assign g4[9] = (~(g2_b[9] | g2_b[11]));
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assign g4[8] = (~(g2_b[8] | g2_b[10]));
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assign g4[7] = (~(g2_b[7] | g2_b[9]));
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assign g4[6] = (~(g2_b[6] | g2_b[8]));
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assign g4[5] = (~(g2_b[5] | g2_b[7]));
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assign g4[4] = (~(g2_b[4] | g2_b[6]));
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assign g4[3] = (~(g2_b[3] | g2_b[5]));
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assign g4[2] = (~(g2_b[2] | g2_b[4]));
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assign g8_b[19] = (~(g4[19]));
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assign g8_b[18] = (~(g4[18]));
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assign g8_b[17] = (~(g4[17]));
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assign g8_b[16] = (~(g4[16]));
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assign g8_b[15] = (~(g4[15] & g4[19]));
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assign g8_b[14] = (~(g4[14] & g4[18]));
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assign g8_b[13] = (~(g4[13] & g4[17]));
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assign g8_b[12] = (~(g4[12] & g4[16]));
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assign g8_b[11] = (~(g4[11] & g4[15]));
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assign g8_b[10] = (~(g4[10] & g4[14]));
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assign g8_b[9] = (~(g4[9] & g4[13]));
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assign g8_b[8] = (~(g4[8] & g4[12]));
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assign g8_b[7] = (~(g4[7] & g4[11]));
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assign g8_b[6] = (~(g4[6] & g4[10]));
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assign g8_b[5] = (~(g4[5] & g4[9]));
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assign g8_b[4] = (~(g4[4] & g4[8]));
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assign g8_b[3] = (~(g4[3] & g4[7]));
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assign g8_b[2] = (~(g4[2] & g4[6]));
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assign g16[19] = (~(g8_b[19]));
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assign g16[18] = (~(g8_b[18]));
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assign g16[17] = (~(g8_b[17]));
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assign g16[16] = (~(g8_b[16]));
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assign g16[15] = (~(g8_b[15]));
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assign g16[14] = (~(g8_b[14]));
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assign g16[13] = (~(g8_b[13]));
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assign g16[12] = (~(g8_b[12]));
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assign g16[11] = (~(g8_b[11] | g8_b[19]));
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assign g16[10] = (~(g8_b[10] | g8_b[18]));
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assign g16[9] = (~(g8_b[9] | g8_b[17]));
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assign g16[8] = (~(g8_b[8] | g8_b[16]));
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assign g16[7] = (~(g8_b[7] | g8_b[15]));
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assign g16[6] = (~(g8_b[6] | g8_b[14]));
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assign g16[5] = (~(g8_b[5] | g8_b[13]));
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assign g16[4] = (~(g8_b[4] | g8_b[12]));
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assign g16[3] = (~(g8_b[3] | g8_b[11]));
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assign g16[2] = (~(g8_b[2] | g8_b[10]));
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assign a_cout_b[19] = (~(g16[19]));
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assign a_cout_b[18] = (~(g16[18]));
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assign a_cout_b[17] = (~(g16[17]));
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assign a_cout_b[16] = (~(g16[16]));
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assign a_cout_b[15] = (~(g16[15]));
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assign a_cout_b[14] = (~(g16[14]));
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assign a_cout_b[13] = (~(g16[13]));
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assign a_cout_b[12] = (~(g16[12]));
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assign a_cout_b[11] = (~(g16[11]));
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assign a_cout_b[10] = (~(g16[10]));
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assign a_cout_b[9] = (~(g16[9]));
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assign a_cout_b[8] = (~(g16[8]));
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assign a_cout_b[7] = (~(g16[7]));
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assign a_cout_b[6] = (~(g16[6]));
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assign a_cout_b[5] = (~(g16[5]));
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assign a_cout_b[4] = (~(g16[4]));
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assign a_cout_b[3] = (~(g16[3] & g16[19]));
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assign a_cout_b[2] = (~(g16[2] & g16[18]));
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//---------------------------------------------------------
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assign a_sum[1:18] = a[1:18];
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assign a_sum[19] = (~a[19]);
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assign o[01:18] = (~(a_sum[01:18] ^ a_cout_b[02:19])); //output
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assign o[19] = a_sum[19]; //output
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endmodule
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