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106 lines
3.5 KiB
Verilog
106 lines
3.5 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_loc8inc_lsb(
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x,
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co_b,
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s0,
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s1
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);
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input [0:4] x; //48 to 52
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output co_b;
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output [0:4] s0;
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output [0:4] s1;
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wire [0:4] x_b;
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wire [0:4] t2_b;
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wire [0:4] t4;
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// FOLDED layout
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// i0_xb i2_xb i4_xb skip skip skip skip
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// i1_xb i3_xb skip skip skip skip skip
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// i0_t2 i2_t2 i4_t2 skip skip skip skip
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// skip i1_t2 i3_t2 skip skip skip skip
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// i0_t2 i2_t2 i4_t2 skip skip skip skip
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// i0_t8 i1_t2 i3_t2 skip skip skip skip
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// i0_s0 i2_s0 i4_s0 skip skip skip skip
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// i1_s0 i3_s0 skip skip skip skip skip
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// i0_s1 i2_s1 i4_s1 skip skip skip skip
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// i1_s1 i3_s1 skip skip skip skip skip
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//-------------------------------
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// buffer off non critical path
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//-------------------------------
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assign x_b[0] = (~x[0]);
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assign x_b[1] = (~x[1]);
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assign x_b[2] = (~x[2]);
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assign x_b[3] = (~x[3]);
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assign x_b[4] = (~x[4]);
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//--------------------------
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// local carry chain
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//--------------------------
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assign t2_b[0] = (~(x[0]));
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assign t2_b[1] = (~(x[1] & x[2]));
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assign t2_b[2] = (~(x[2] & x[3]));
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assign t2_b[3] = (~(x[3] & x[4]));
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assign t2_b[4] = (~(x[4]));
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assign t4[0] = (~(t2_b[0]));
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assign t4[1] = (~(t2_b[1] | t2_b[3]));
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assign t4[2] = (~(t2_b[2] | t2_b[4]));
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assign t4[3] = (~(t2_b[3]));
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assign t4[4] = (~(t2_b[4]));
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assign co_b = (~(t4[0] & t4[1]));
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//------------------------
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// sum generation
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//------------------------
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assign s0[0] = (~(x_b[0]));
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assign s0[1] = (~(x_b[1]));
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assign s0[2] = (~(x_b[2]));
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assign s0[3] = (~(x_b[3]));
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assign s0[4] = (~(x_b[4]));
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assign s1[0] = (~(x_b[0] ^ t4[1]));
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assign s1[1] = (~(x_b[1] ^ t4[2]));
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assign s1[2] = (~(x_b[2] ^ t4[3]));
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assign s1[3] = (~(x_b[3] ^ t4[4]));
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assign s1[4] = (~(t4[4]));
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endmodule
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