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179 lines
6.0 KiB
Verilog
179 lines
6.0 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_lza_ej(
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effsub,
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sum,
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car,
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lzo_b,
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edge_t
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);
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input effsub;
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input [0:162] sum;
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input [53:162] car;
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input [0:162] lzo_b;
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output [0:162] edge_t;
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// generic 3 bit edge ::
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// P G !Z
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// P Z !G
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// !P G !G
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// !P Z !Z
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire [0:52] x0;
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wire [0:52] x1;
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wire [0:52] x2;
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wire [0:52] x1_b;
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wire [0:52] ej_b;
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wire [53:162] g_b;
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wire [53:162] z;
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wire [53:162] p;
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wire [53:162] g;
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wire [53:162] z_b;
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wire [53:162] p_b;
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wire sum_52_b;
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wire lzo_54;
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wire [55:162] gz;
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wire [55:162] zg;
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wire [55:162] gg;
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wire [55:162] zz;
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wire [53:162] e0_b;
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wire [53:162] e1_b;
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wire [54:54] e2_b;
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wire unused;
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// these are different heights for different bits ... place them as seperate columns
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// for 0 :52
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// for 53
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// for 54
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// for 55
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// for 56:162
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assign unused = g[54] | z_b[53] | z_b[162] | p_b[161] | p_b[162];
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//-------------------------------------------
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// (0:52) only one data input
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//-------------------------------------------
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assign x0[0:52] = {tidn, effsub, sum[0:50]}; // just a rename
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assign x1[0:52] = {effsub, sum[0:51]}; // just a rename
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assign x2[0:52] = sum[0:52]; // just a rename
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assign x1_b[0:52] = (~x1[0:52]);
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assign ej_b[0:52] = (~(x1_b[0:52] & (x0[0:52] | x2[0:52])));
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assign edge_t[0:52] = (~(ej_b[0:52] & lzo_b[0:52]));
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//-----------------------------------------------------------------
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// (53) psuedo bit
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//-----------------------------------------------------------------
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assign g_b[53] = (~(sum[53] & car[53]));
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assign z[53] = (~(sum[53] | car[53]));
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assign p[53] = (sum[53] ^ car[53]);
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assign g[53] = (~(g_b[53]));
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assign z_b[53] = (~(z[53])); //UNUSED
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assign p_b[53] = (~(p[53]));
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assign sum_52_b = (~(sum[52]));
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assign e0_b[53] = (~(sum[51] & sum_52_b));
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assign e1_b[53] = (~(sum_52_b & g[53]));
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assign edge_t[53] = (~(lzo_b[53] & e0_b[53] & e1_b[53])); //output
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//-----------------------------------------------------------------
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// (54) pseudo bit + 1
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//-----------------------------------------------------------------
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assign g_b[54] = (~(sum[54] & car[54]));
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assign z[54] = (~(sum[54] | car[54]));
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assign p[54] = (sum[54] ^ car[54]);
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assign g[54] = (~(g_b[54])); //UNUSED
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assign z_b[54] = (~(z[54]));
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assign p_b[54] = (~(p[54]));
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assign lzo_54 = (~lzo_b[54]);
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assign e0_b[54] = (~(sum_52_b & p[53] & z_b[54])); //really is p54 (demotes to z54)
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assign e1_b[54] = (~(sum[52] & p[53] & g_b[54])); //really is p54 (demotes to z54)
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assign e2_b[54] = (~((sum[52] & z[53]) | lzo_54));
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assign edge_t[54] = (~(e0_b[54] & e1_b[54] & e2_b[54])); //output
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//-----------------------------------------------------------------
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// (55) pseudo bit + 2
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//-----------------------------------------------------------------
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assign g_b[55] = (~(sum[55] & car[55]));
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assign z[55] = (~(sum[55] | car[55]));
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assign p[55] = (sum[55] ^ car[55]);
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assign g[55] = (~(g_b[55]));
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assign z_b[55] = (~(z[55]));
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assign p_b[55] = (~(p[55]));
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assign gz[55] = (~(g_b[54] | z[55]));
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assign zg[55] = (~(z_b[54] | g[55]));
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assign gg[55] = (~(g_b[54] | g[55]));
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assign zz[55] = (~(z_b[54] | z[55]));
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assign e1_b[55] = (~(p_b[53] & (gz[55] | zg[55]))); // P is flipped for psuedo bit
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assign e0_b[55] = (~(p[53] & (gg[55] | zz[55]))); // P is flipped for psuedo bit
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assign edge_t[55] = (~(e0_b[55] & e1_b[55] & lzo_b[55])); //output
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//-----------------------------------------------------------------
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// (56:162) normal 2 input edge_t
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//-----------------------------------------------------------------
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assign g_b[56:162] = (~(sum[56:162] & car[56:162]));
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assign z[56:162] = (~(sum[56:162] | car[56:162]));
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assign p[56:162] = (sum[56:162] ^ car[56:162]);
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assign g[56:162] = (~(g_b[56:162]));
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assign z_b[56:162] = (~(z[56:162])); //162 unused
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assign p_b[56:162] = (~(p[56:162])); //161,162 unused
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assign gz[56:162] = (~(g_b[55:161] | z[56:162]));
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assign zg[56:162] = (~(z_b[55:161] | g[56:162]));
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assign gg[56:162] = (~(g_b[55:161] | g[56:162]));
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assign zz[56:162] = (~(z_b[55:161] | z[56:162]));
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assign e1_b[56:162] = (~(p[54:160] & (gz[56:162] | zg[56:162])));
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assign e0_b[56:162] = (~(p_b[54:160] & (gg[56:162] | zz[56:162])));
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assign edge_t[56:162] = (~(e0_b[56:162] & e1_b[56:162] & lzo_b[56:162])); //output
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endmodule
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