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233 lines
12 KiB
Verilog
233 lines
12 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// VHDL 1076 Macro Expander C version 07/11/00
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// job was run on Fri Mar 25 11:38:23 2011
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//********************************************************************
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//*
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//* TITLE: IU Branch Decode
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//*
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//* NAME: iuq_bd.vhdl
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//*
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//*********************************************************************
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module iuq_bd(
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instruction,
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instruction_next,
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branch_decode,
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bp_bc_en,
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bp_bclr_en,
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bp_bcctr_en,
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bp_sw_en
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);
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//parameter `GPR_WIDTH = 64;
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`include "tri_a2o.vh"
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(* analysis_not_referenced="<12:20>true" *)
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input [0:31] instruction;
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(* analysis_not_referenced="<6:7>,<9:10>,<14:20>,<31>true" *)
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input [0:31] instruction_next;
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output [0:3] branch_decode;
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input bp_bc_en;
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input bp_bclr_en;
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input bp_bcctr_en;
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input bp_sw_en;
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wire [1:12] MICROCODE_PT;
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wire core64;
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wire to_uc;
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//architecture iuq_bd of iuq_bd is
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wire b;
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wire bc;
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wire bclr;
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wire bcctr;
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wire bctar;
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wire br_val;
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wire [0:4] bo;
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wire hint;
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wire hint_val;
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wire cmpi;
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wire cmpli;
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wire cmp;
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wire cmpl;
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wire [0:2] bf;
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wire next_bc;
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wire next_bclr;
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wire next_bcctr;
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wire next_bctar;
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wire [0:2] next_bi;
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wire next_ctr;
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wire fuse_val;
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//@@ START OF EXECUTABLE CODE FOR IUQ_BD
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//begin
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assign b = instruction[0:5] == 6'b010010;
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assign bc = bp_bc_en & instruction[0:5] == 6'b010000;
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assign bclr = bp_bclr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b0000010000;
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assign bcctr = bp_bcctr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b1000010000;
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assign bctar = bp_bcctr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b1000110000;
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assign br_val = b | bc | bclr | bcctr | bctar;
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assign bo[0:4] = instruction[6:10];
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assign hint_val = (bo[0] & bo[2]) | (bp_sw_en & ((bo[0] == 1'b0 & bo[2] == 1'b1 & bo[3] == 1'b1) | (bo[0] == 1'b1 & bo[2] == 1'b0 & bo[1] == 1'b1)));
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assign hint = (bo[0] & bo[2]) | bo[4];
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assign branch_decode[0:3] = {br_val, (b | to_uc), ((br_val & hint_val) | fuse_val), hint};
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//------------------
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// fusion predecode
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//------------------
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assign cmpi = instruction[0:5] == 6'b001011;
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assign cmpli = instruction[0:5] == 6'b001010;
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assign cmp = instruction[0:5] == 6'b011111 & instruction[21:30] == 10'b0000000000;
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assign cmpl = instruction[0:5] == 6'b011111 & instruction[21:30] == 10'b0000100000;
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assign bf[0:2] = instruction[6:8];
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assign next_bc = instruction_next[0:5] == 6'b010000;
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assign next_bclr = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b0000010000;
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assign next_bcctr = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b1000010000;
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assign next_bctar = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b1000110000;
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assign next_bi[0:2] = instruction_next[11:13];
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assign next_ctr = instruction_next[8] == 1'b0;
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//remove update LR cases for now
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assign fuse_val = (bf[0:2] == next_bi[0:2]) & (((cmpi | cmpli) & (next_bc | next_bcctr | ((next_bclr | next_bctar) & (~next_ctr)))) | ((cmp | cmpl) & (((next_bc) & (~next_ctr)))));
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//------------------
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// ucode predecode
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//------------------
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//64-bit core
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generate
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if (`GPR_WIDTH == 64)
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begin : c64
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assign core64 = 1'b1;
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end
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endgenerate
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//32-bit core
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generate
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if (`GPR_WIDTH == 32)
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begin : c32
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assign core64 = 1'b0;
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end
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endgenerate
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/*
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//table_start
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?TABLE microcode LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET);
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*INPUTS*=====================*OUTPUTS*==*
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| | |
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| core64 | |
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| | | |
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| | instruction | to_uc |
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| | | instruction | | |
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| | | | instruction | | |
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| | | | | | | |
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| | | 1 22222222233 | | |
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| | 012345 1 12345678901 | | |
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*TYPE*=======================+==========+
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| S PPPPPP P PPPPPPPPPPP | S |
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*TERMS*======================+==========+
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| . 100011 . ........... | 1 | lbzu
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| . 011111 . 0001110111. | 1 | lbzux
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| 1 111010 . .........01 | 1 | ldu
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| 1 011111 . 0000110101. | 1 | ldux
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| . 101011 . ........... | 1 | lhau
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| . 011111 . 0101110111. | 1 | lhaux
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| . 101001 . ........... | 1 | lhzu
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| . 011111 . 0100110111. | 1 | lhzux
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| . 101110 . ........... | 1 | lmw
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| . 011111 . 1001010101. | 1 | lswi
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| . 011111 . 1000010101. | 1 | lswx
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| 1 011111 . 0101110101. | 1 | lwaux
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| . 100001 . ........... | 1 | lwzu
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| . 011111 . 0000110111. | 1 | lwzux
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| . 110001 . ........... | 1 | lfsu
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| . 011111 . 1000110111. | 1 | lfsux
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| . 110011 . ........... | 1 | lfdu
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| . 011111 . 1001110111. | 1 | lfdux
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| . 011111 . 1000000000. | 1 | mcrxr
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| . 011111 0 0000010011. | 1 | mfcr
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| . 011111 0 0010010000. | 1 | mtcrf
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| . 101111 . ........... | 1 | stmw
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| . 011111 . 1011010101. | 1 | stswi
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| . 011111 . 1010010101. | 1 | stswx
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*END*========================+==========+
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?TABLE END microcode ;
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//table_end
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*/
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//assign_start
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//
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// Final Table Listing
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// *INPUTS*=====================*OUTPUTS*==*
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// | | |
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// | core64 | |
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// | | | |
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// | | instruction | to_uc |
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// | | | instruction | | |
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// | | | | instruction | | |
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// | | | | | | | |
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// | | | 1 22222222233 | | |
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// | | 012345 1 12345678901 | | |
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// *TYPE*=======================+==========+
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// | S PPPPPP P PPPPPPPPPPP | S |
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// *POLARITY*------------------>| + |
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// *PHASE*--------------------->| T |
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// *TERMS*======================+==========+
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// 1 | - 011111 0 0010010000- | 1 |
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// 2 | - 011111 - 1000000000- | 1 |
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// 3 | 1 011111 - 01011101-1- | 1 |
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// 4 | - 011111 0 0000010011- | 1 |
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// 5 | 1 011111 - 00001101-1- | 1 |
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// 6 | - 011111 - 10--010101- | 1 |
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// 7 | - 011111 - 0-0-110111- | 1 |
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// 8 | - 011111 - -00-110111- | 1 |
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// 9 | 1 111010 - ---------01 | 1 |
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// 10 | - 1-00-1 - ----------- | 1 |
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// 11 | - 10-0-1 - ----------- | 1 |
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// 12 | - 10111- - ----------- | 1 |
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// *=======================================*
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//
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// Table MICROCODE Signal Assignments for Product Terms
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assign MICROCODE_PT[1] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[11], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 17'b01111100010010000);
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assign MICROCODE_PT[2] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 16'b0111111000000000);
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assign MICROCODE_PT[3] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[30]}) === 16'b1011111010111011);
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assign MICROCODE_PT[4] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[11], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 17'b01111100000010011);
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assign MICROCODE_PT[5] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[30]}) === 16'b1011111000011011);
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assign MICROCODE_PT[6] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111110010101);
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assign MICROCODE_PT[7] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[23], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111100110111);
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assign MICROCODE_PT[8] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[22], instruction[23], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111100110111);
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assign MICROCODE_PT[9] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[30], instruction[31]}) === 9'b111101001);
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assign MICROCODE_PT[10] = (({instruction[0], instruction[2], instruction[3], instruction[5]}) === 4'b1001);
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assign MICROCODE_PT[11] = (({instruction[0], instruction[1], instruction[3], instruction[5]}) === 4'b1001);
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assign MICROCODE_PT[12] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4]}) === 5'b10111);
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// Table MICROCODE Signal Assignments for Outputs
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assign to_uc = (MICROCODE_PT[1] | MICROCODE_PT[2] | MICROCODE_PT[3] | MICROCODE_PT[4] | MICROCODE_PT[5] | MICROCODE_PT[6] | MICROCODE_PT[7] | MICROCODE_PT[8] | MICROCODE_PT[9] | MICROCODE_PT[10] | MICROCODE_PT[11] | MICROCODE_PT[12]);
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//assign_end
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endmodule
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