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86 lines
2.9 KiB
Verilog
86 lines
2.9 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: Saturating Incrementer
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module iuq_rn_map_inc #(
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parameter SIZE = 7,
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parameter WRAP = 40)
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(
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inc,
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i,
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o
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);
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input [0:1] inc;
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input [0:SIZE-1] i;
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output [0:SIZE-1] o;
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localparam [0:31] value_1 = 32'h00000001;
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wire [0:SIZE] a;
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wire [0:SIZE] b;
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wire [0:SIZE] rslt;
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wire rollover;
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wire rollover_m1;
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wire inc_1;
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wire inc_2;
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wire [0:1] wrap_sel;
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// Increment by 1 or 2.
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// Go back to zero at WRAP
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// Flip bit zero when a rollover occurs
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// eg 0...39, 64..103
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assign a = {i[0:SIZE - 1], inc[1]};
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assign b = {{SIZE-1{1'b0}}, inc[0], inc[1]};
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assign rslt = a + b;
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assign rollover = i[0:SIZE - 1] == WRAP;
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assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1;
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assign inc_1 = inc[0] ^ inc[1];
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assign inc_2 = inc[0] & inc[1];
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assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2);
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assign wrap_sel[1] = rollover & inc_2;
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assign o[0:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? {SIZE{1'b0}} :
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(wrap_sel[0:1] == 2'b01) ? value_1[32-SIZE:31] :
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rslt[0:SIZE - 1];
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endmodule
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