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981 lines
50 KiB
Verilog
981 lines
50 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//********************************************************************
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//*
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//* TITLE:
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//*
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//* NAME: iuq_rn_top.vhdl
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//*
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//*********************************************************************
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`include "tri_a2o.vh"
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module iuq_rn_top(
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inout vdd,
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inout gnd,
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input [0:`NCLK_WIDTH-1] nclk,
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input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types
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input pc_iu_sg_2,
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input clkoff_b,
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input act_dis,
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input tc_ac_ccflush_dc,
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input d_mode,
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input delay_lclkr,
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input mpw1_b,
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input mpw2_b,
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input [0:1] func_scan_in,
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output [0:1] func_scan_out,
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//-------------------------------
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// Performance interface with I$
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//-------------------------------
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input pc_iu_event_bus_enable,
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output perf_iu5_stall,
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output perf_iu5_cpl_credit_stall,
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output perf_iu5_gpr_credit_stall,
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output perf_iu5_cr_credit_stall,
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output perf_iu5_lr_credit_stall,
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output perf_iu5_ctr_credit_stall,
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output perf_iu5_xer_credit_stall,
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output perf_iu5_br_hold_stall,
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output perf_iu5_axu_hold_stall,
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//-----------------------------
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// Inputs to rename from decode
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//-----------------------------
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input fdec_frn_iu5_i0_vld,
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input [0:2] fdec_frn_iu5_i0_ucode,
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input fdec_frn_iu5_i0_2ucode,
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input fdec_frn_iu5_i0_fuse_nop,
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input fdec_frn_iu5_i0_rte_lq,
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input fdec_frn_iu5_i0_rte_sq,
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input fdec_frn_iu5_i0_rte_fx0,
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input fdec_frn_iu5_i0_rte_fx1,
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input fdec_frn_iu5_i0_rte_axu0,
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input fdec_frn_iu5_i0_rte_axu1,
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input fdec_frn_iu5_i0_valop,
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input fdec_frn_iu5_i0_ord,
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input fdec_frn_iu5_i0_cord,
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input [0:2] fdec_frn_iu5_i0_error,
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input fdec_frn_iu5_i0_btb_entry,
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input [0:1] fdec_frn_iu5_i0_btb_hist,
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input fdec_frn_iu5_i0_bta_val,
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input [0:19] fdec_frn_iu5_i0_fusion,
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input fdec_frn_iu5_i0_spec,
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input fdec_frn_iu5_i0_type_fp,
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input fdec_frn_iu5_i0_type_ap,
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input fdec_frn_iu5_i0_type_spv,
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input fdec_frn_iu5_i0_type_st,
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input fdec_frn_iu5_i0_async_block,
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input fdec_frn_iu5_i0_np1_flush,
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input fdec_frn_iu5_i0_core_block,
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input fdec_frn_iu5_i0_isram,
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input fdec_frn_iu5_i0_isload,
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input fdec_frn_iu5_i0_isstore,
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input [0:31] fdec_frn_iu5_i0_instr,
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input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar,
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input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta,
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input fdec_frn_iu5_i0_br_pred,
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input fdec_frn_iu5_i0_bh_update,
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input [0:1] fdec_frn_iu5_i0_bh0_hist,
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input [0:1] fdec_frn_iu5_i0_bh1_hist,
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input [0:1] fdec_frn_iu5_i0_bh2_hist,
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input [0:17] fdec_frn_iu5_i0_gshare,
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input [0:2] fdec_frn_iu5_i0_ls_ptr,
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input fdec_frn_iu5_i0_match,
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input [0:3] fdec_frn_iu5_i0_ilat,
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input fdec_frn_iu5_i0_t1_v,
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input [0:2] fdec_frn_iu5_i0_t1_t,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a,
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input fdec_frn_iu5_i0_t2_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a,
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input [0:2] fdec_frn_iu5_i0_t2_t,
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input fdec_frn_iu5_i0_t3_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a,
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input [0:2] fdec_frn_iu5_i0_t3_t,
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input fdec_frn_iu5_i0_s1_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a,
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input [0:2] fdec_frn_iu5_i0_s1_t,
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input fdec_frn_iu5_i0_s2_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a,
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input [0:2] fdec_frn_iu5_i0_s2_t,
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input fdec_frn_iu5_i0_s3_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a,
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input [0:2] fdec_frn_iu5_i0_s3_t,
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input fdec_frn_iu5_i1_vld,
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input [0:2] fdec_frn_iu5_i1_ucode,
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input fdec_frn_iu5_i1_fuse_nop,
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input fdec_frn_iu5_i1_rte_lq,
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input fdec_frn_iu5_i1_rte_sq,
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input fdec_frn_iu5_i1_rte_fx0,
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input fdec_frn_iu5_i1_rte_fx1,
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input fdec_frn_iu5_i1_rte_axu0,
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input fdec_frn_iu5_i1_rte_axu1,
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input fdec_frn_iu5_i1_valop,
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input fdec_frn_iu5_i1_ord,
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input fdec_frn_iu5_i1_cord,
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input [0:2] fdec_frn_iu5_i1_error,
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input fdec_frn_iu5_i1_btb_entry,
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input [0:1] fdec_frn_iu5_i1_btb_hist,
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input fdec_frn_iu5_i1_bta_val,
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input [0:19] fdec_frn_iu5_i1_fusion,
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input fdec_frn_iu5_i1_spec,
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input fdec_frn_iu5_i1_type_fp,
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input fdec_frn_iu5_i1_type_ap,
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input fdec_frn_iu5_i1_type_spv,
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input fdec_frn_iu5_i1_type_st,
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input fdec_frn_iu5_i1_async_block,
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input fdec_frn_iu5_i1_np1_flush,
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input fdec_frn_iu5_i1_core_block,
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input fdec_frn_iu5_i1_isram,
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input fdec_frn_iu5_i1_isload,
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input fdec_frn_iu5_i1_isstore,
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input [0:31] fdec_frn_iu5_i1_instr,
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input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar,
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input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta,
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input fdec_frn_iu5_i1_br_pred,
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input fdec_frn_iu5_i1_bh_update,
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input [0:1] fdec_frn_iu5_i1_bh0_hist,
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input [0:1] fdec_frn_iu5_i1_bh1_hist,
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input [0:1] fdec_frn_iu5_i1_bh2_hist,
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input [0:17] fdec_frn_iu5_i1_gshare,
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input [0:2] fdec_frn_iu5_i1_ls_ptr,
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input fdec_frn_iu5_i1_match,
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input [0:3] fdec_frn_iu5_i1_ilat,
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input fdec_frn_iu5_i1_t1_v,
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input [0:2] fdec_frn_iu5_i1_t1_t,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a,
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input fdec_frn_iu5_i1_t2_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a,
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input [0:2] fdec_frn_iu5_i1_t2_t,
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input fdec_frn_iu5_i1_t3_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a,
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input [0:2] fdec_frn_iu5_i1_t3_t,
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input fdec_frn_iu5_i1_s1_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a,
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input [0:2] fdec_frn_iu5_i1_s1_t,
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input fdec_frn_iu5_i1_s2_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a,
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input [0:2] fdec_frn_iu5_i1_s2_t,
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input fdec_frn_iu5_i1_s3_v,
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input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a,
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input [0:2] fdec_frn_iu5_i1_s3_t,
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//-----------------------------
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// SPR values
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//-----------------------------
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input spr_high_pri_mask,
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input spr_cpcr_we,
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input [0:6] spr_cpcr3_cp_cnt,
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input [0:6] spr_cpcr5_cp_cnt,
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input spr_single_issue,
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//-----------------------------
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// Stall to decode
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//-----------------------------
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output frn_fdec_iu5_stall,
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//-----------------------------
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// Stall from dispatch
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//-----------------------------
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input fdis_frn_iu6_stall,
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//----------------------------
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// Completion Interface
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//----------------------------
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input cp_rn_i0_axu_exception_val,
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input [0:3] cp_rn_i0_axu_exception,
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input cp_rn_i1_axu_exception_val,
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input [0:3] cp_rn_i1_axu_exception,
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input cp_rn_empty,
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input cp_rn_i0_v,
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input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag,
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input cp_rn_i0_t1_v,
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input [0:2] cp_rn_i0_t1_t,
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input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p,
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input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a,
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input cp_rn_i0_t2_v,
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input [0:2] cp_rn_i0_t2_t,
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input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p,
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input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a,
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input cp_rn_i0_t3_v,
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input [0:2] cp_rn_i0_t3_t,
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input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p,
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input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a,
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input cp_rn_i1_v,
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input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag,
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input cp_rn_i1_t1_v,
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input [0:2] cp_rn_i1_t1_t,
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input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p,
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input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a,
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input cp_rn_i1_t2_v,
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input [0:2] cp_rn_i1_t2_t,
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input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p,
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input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a,
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input cp_rn_i1_t3_v,
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input [0:2] cp_rn_i1_t3_t,
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input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p,
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input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a,
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input cp_flush,
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input cp_flush_into_uc,
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input br_iu_redirect,
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input cp_rn_uc_credit_free,
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//----------------------------------------------------------------
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// Interface to reservation station - Completion is snooping also
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//----------------------------------------------------------------
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output frn_fdis_iu6_i0_vld,
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output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag,
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output [0:2] frn_fdis_iu6_i0_ucode,
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output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt,
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output frn_fdis_iu6_i0_2ucode,
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output frn_fdis_iu6_i0_fuse_nop,
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output frn_fdis_iu6_i0_rte_lq,
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output frn_fdis_iu6_i0_rte_sq,
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output frn_fdis_iu6_i0_rte_fx0,
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output frn_fdis_iu6_i0_rte_fx1,
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output frn_fdis_iu6_i0_rte_axu0,
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output frn_fdis_iu6_i0_rte_axu1,
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output frn_fdis_iu6_i0_valop,
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output frn_fdis_iu6_i0_ord,
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output frn_fdis_iu6_i0_cord,
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output [0:2] frn_fdis_iu6_i0_error,
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output frn_fdis_iu6_i0_btb_entry,
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output [0:1] frn_fdis_iu6_i0_btb_hist,
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output frn_fdis_iu6_i0_bta_val,
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output [0:19] frn_fdis_iu6_i0_fusion,
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output frn_fdis_iu6_i0_spec,
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output frn_fdis_iu6_i0_type_fp,
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output frn_fdis_iu6_i0_type_ap,
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output frn_fdis_iu6_i0_type_spv,
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output frn_fdis_iu6_i0_type_st,
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output frn_fdis_iu6_i0_async_block,
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output frn_fdis_iu6_i0_np1_flush,
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output frn_fdis_iu6_i0_core_block,
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output frn_fdis_iu6_i0_isram,
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output frn_fdis_iu6_i0_isload,
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output frn_fdis_iu6_i0_isstore,
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output [0:31] frn_fdis_iu6_i0_instr,
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output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar,
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output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta,
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output frn_fdis_iu6_i0_br_pred,
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output frn_fdis_iu6_i0_bh_update,
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output [0:1] frn_fdis_iu6_i0_bh0_hist,
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output [0:1] frn_fdis_iu6_i0_bh1_hist,
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output [0:1] frn_fdis_iu6_i0_bh2_hist,
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output [0:17] frn_fdis_iu6_i0_gshare,
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output [0:2] frn_fdis_iu6_i0_ls_ptr,
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output frn_fdis_iu6_i0_match,
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output [0:3] frn_fdis_iu6_i0_ilat,
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output frn_fdis_iu6_i0_t1_v,
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output [0:2] frn_fdis_iu6_i0_t1_t,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p,
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output frn_fdis_iu6_i0_t2_v,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p,
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output [0:2] frn_fdis_iu6_i0_t2_t,
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output frn_fdis_iu6_i0_t3_v,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p,
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output [0:2] frn_fdis_iu6_i0_t3_t,
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output frn_fdis_iu6_i0_s1_v,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p,
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output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag,
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output [0:2] frn_fdis_iu6_i0_s1_t,
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output frn_fdis_iu6_i0_s2_v,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p,
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output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag,
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output [0:2] frn_fdis_iu6_i0_s2_t,
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output frn_fdis_iu6_i0_s3_v,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a,
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output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p,
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output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag,
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output [0:2] frn_fdis_iu6_i0_s3_t,
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output frn_fdis_iu6_i1_vld,
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output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag,
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output [0:2] frn_fdis_iu6_i1_ucode,
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output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt,
|
|
output frn_fdis_iu6_i1_fuse_nop,
|
|
output frn_fdis_iu6_i1_rte_lq,
|
|
output frn_fdis_iu6_i1_rte_sq,
|
|
output frn_fdis_iu6_i1_rte_fx0,
|
|
output frn_fdis_iu6_i1_rte_fx1,
|
|
output frn_fdis_iu6_i1_rte_axu0,
|
|
output frn_fdis_iu6_i1_rte_axu1,
|
|
output frn_fdis_iu6_i1_valop,
|
|
output frn_fdis_iu6_i1_ord,
|
|
output frn_fdis_iu6_i1_cord,
|
|
output [0:2] frn_fdis_iu6_i1_error,
|
|
output frn_fdis_iu6_i1_btb_entry,
|
|
output [0:1] frn_fdis_iu6_i1_btb_hist,
|
|
output frn_fdis_iu6_i1_bta_val,
|
|
output [0:19] frn_fdis_iu6_i1_fusion,
|
|
output frn_fdis_iu6_i1_spec,
|
|
output frn_fdis_iu6_i1_type_fp,
|
|
output frn_fdis_iu6_i1_type_ap,
|
|
output frn_fdis_iu6_i1_type_spv,
|
|
output frn_fdis_iu6_i1_type_st,
|
|
output frn_fdis_iu6_i1_async_block,
|
|
output frn_fdis_iu6_i1_np1_flush,
|
|
output frn_fdis_iu6_i1_core_block,
|
|
output frn_fdis_iu6_i1_isram,
|
|
output frn_fdis_iu6_i1_isload,
|
|
output frn_fdis_iu6_i1_isstore,
|
|
output [0:31] frn_fdis_iu6_i1_instr,
|
|
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar,
|
|
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta,
|
|
output frn_fdis_iu6_i1_br_pred,
|
|
output frn_fdis_iu6_i1_bh_update,
|
|
output [0:1] frn_fdis_iu6_i1_bh0_hist,
|
|
output [0:1] frn_fdis_iu6_i1_bh1_hist,
|
|
output [0:1] frn_fdis_iu6_i1_bh2_hist,
|
|
output [0:17] frn_fdis_iu6_i1_gshare,
|
|
output [0:2] frn_fdis_iu6_i1_ls_ptr,
|
|
output frn_fdis_iu6_i1_match,
|
|
output [0:3] frn_fdis_iu6_i1_ilat,
|
|
output frn_fdis_iu6_i1_t1_v,
|
|
output [0:2] frn_fdis_iu6_i1_t1_t,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p,
|
|
output frn_fdis_iu6_i1_t2_v,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p,
|
|
output [0:2] frn_fdis_iu6_i1_t2_t,
|
|
output frn_fdis_iu6_i1_t3_v,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p,
|
|
output [0:2] frn_fdis_iu6_i1_t3_t,
|
|
output frn_fdis_iu6_i1_s1_v,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p,
|
|
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag,
|
|
output [0:2] frn_fdis_iu6_i1_s1_t,
|
|
output frn_fdis_iu6_i1_s1_dep_hit,
|
|
output frn_fdis_iu6_i1_s2_v,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p,
|
|
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag,
|
|
output [0:2] frn_fdis_iu6_i1_s2_t,
|
|
output frn_fdis_iu6_i1_s2_dep_hit,
|
|
output frn_fdis_iu6_i1_s3_v,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a,
|
|
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p,
|
|
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag,
|
|
output [0:2] frn_fdis_iu6_i1_s3_t,
|
|
output frn_fdis_iu6_i1_s3_dep_hit
|
|
|
|
);
|
|
|
|
wire au_iu_iu5_stall;
|
|
wire iu_au_iu5_send_ok;
|
|
wire [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0;
|
|
wire [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1;
|
|
wire au_iu_iu5_axu0_send_ok;
|
|
wire au_iu_iu5_axu1_send_ok;
|
|
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p;
|
|
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag;
|
|
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag;
|
|
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p;
|
|
wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p;
|
|
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag;
|
|
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag;
|
|
wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag;
|
|
wire au_iu_iu5_i1_s1_dep_hit;
|
|
wire au_iu_iu5_i1_s2_dep_hit;
|
|
wire au_iu_iu5_i1_s3_dep_hit;
|
|
|
|
|
|
iuq_rn fx_rn0(
|
|
.vdd(vdd),
|
|
.gnd(gnd),
|
|
.nclk(nclk),
|
|
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
|
|
.pc_iu_sg_2(pc_iu_sg_2),
|
|
.clkoff_b(clkoff_b),
|
|
.act_dis(act_dis),
|
|
.tc_ac_ccflush_dc(tc_ac_ccflush_dc),
|
|
.d_mode(d_mode),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.func_scan_in(func_scan_in[0]),
|
|
.func_scan_out(func_scan_out[0]),
|
|
|
|
//-------------------------------
|
|
// Performance interface with I$
|
|
//-------------------------------
|
|
.pc_iu_event_bus_enable(pc_iu_event_bus_enable),
|
|
.perf_iu5_stall(perf_iu5_stall),
|
|
.perf_iu5_cpl_credit_stall(perf_iu5_cpl_credit_stall),
|
|
.perf_iu5_gpr_credit_stall(perf_iu5_gpr_credit_stall),
|
|
.perf_iu5_cr_credit_stall(perf_iu5_cr_credit_stall),
|
|
.perf_iu5_lr_credit_stall(perf_iu5_lr_credit_stall),
|
|
.perf_iu5_ctr_credit_stall(perf_iu5_ctr_credit_stall),
|
|
.perf_iu5_xer_credit_stall(perf_iu5_xer_credit_stall),
|
|
.perf_iu5_br_hold_stall(perf_iu5_br_hold_stall),
|
|
.perf_iu5_axu_hold_stall(perf_iu5_axu_hold_stall),
|
|
|
|
//-----------------------------
|
|
// Inputs to rename from decode
|
|
//-----------------------------
|
|
.fdec_frn_iu5_i0_vld(fdec_frn_iu5_i0_vld),
|
|
.fdec_frn_iu5_i0_ucode(fdec_frn_iu5_i0_ucode),
|
|
.fdec_frn_iu5_i0_2ucode(fdec_frn_iu5_i0_2ucode),
|
|
.fdec_frn_iu5_i0_fuse_nop(fdec_frn_iu5_i0_fuse_nop),
|
|
.fdec_frn_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq),
|
|
.fdec_frn_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq),
|
|
.fdec_frn_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0),
|
|
.fdec_frn_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1),
|
|
.fdec_frn_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0),
|
|
.fdec_frn_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1),
|
|
.fdec_frn_iu5_i0_valop(fdec_frn_iu5_i0_valop),
|
|
.fdec_frn_iu5_i0_ord(fdec_frn_iu5_i0_ord),
|
|
.fdec_frn_iu5_i0_cord(fdec_frn_iu5_i0_cord),
|
|
.fdec_frn_iu5_i0_error(fdec_frn_iu5_i0_error),
|
|
.fdec_frn_iu5_i0_btb_entry(fdec_frn_iu5_i0_btb_entry),
|
|
.fdec_frn_iu5_i0_btb_hist(fdec_frn_iu5_i0_btb_hist),
|
|
.fdec_frn_iu5_i0_bta_val(fdec_frn_iu5_i0_bta_val),
|
|
.fdec_frn_iu5_i0_fusion(fdec_frn_iu5_i0_fusion),
|
|
.fdec_frn_iu5_i0_spec(fdec_frn_iu5_i0_spec),
|
|
.fdec_frn_iu5_i0_type_fp(fdec_frn_iu5_i0_type_fp),
|
|
.fdec_frn_iu5_i0_type_ap(fdec_frn_iu5_i0_type_ap),
|
|
.fdec_frn_iu5_i0_type_spv(fdec_frn_iu5_i0_type_spv),
|
|
.fdec_frn_iu5_i0_type_st(fdec_frn_iu5_i0_type_st),
|
|
.fdec_frn_iu5_i0_async_block(fdec_frn_iu5_i0_async_block),
|
|
.fdec_frn_iu5_i0_np1_flush(fdec_frn_iu5_i0_np1_flush),
|
|
.fdec_frn_iu5_i0_core_block(fdec_frn_iu5_i0_core_block),
|
|
.fdec_frn_iu5_i0_isram(fdec_frn_iu5_i0_isram),
|
|
.fdec_frn_iu5_i0_isload(fdec_frn_iu5_i0_isload),
|
|
.fdec_frn_iu5_i0_isstore(fdec_frn_iu5_i0_isstore),
|
|
.fdec_frn_iu5_i0_instr(fdec_frn_iu5_i0_instr),
|
|
.fdec_frn_iu5_i0_ifar(fdec_frn_iu5_i0_ifar),
|
|
.fdec_frn_iu5_i0_bta(fdec_frn_iu5_i0_bta),
|
|
.fdec_frn_iu5_i0_br_pred(fdec_frn_iu5_i0_br_pred),
|
|
.fdec_frn_iu5_i0_bh_update(fdec_frn_iu5_i0_bh_update),
|
|
.fdec_frn_iu5_i0_bh0_hist(fdec_frn_iu5_i0_bh0_hist),
|
|
.fdec_frn_iu5_i0_bh1_hist(fdec_frn_iu5_i0_bh1_hist),
|
|
.fdec_frn_iu5_i0_bh2_hist(fdec_frn_iu5_i0_bh2_hist),
|
|
.fdec_frn_iu5_i0_gshare(fdec_frn_iu5_i0_gshare),
|
|
.fdec_frn_iu5_i0_ls_ptr(fdec_frn_iu5_i0_ls_ptr),
|
|
.fdec_frn_iu5_i0_match(fdec_frn_iu5_i0_match),
|
|
.fdec_frn_iu5_i0_ilat(fdec_frn_iu5_i0_ilat),
|
|
.fdec_frn_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v),
|
|
.fdec_frn_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t),
|
|
.fdec_frn_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a),
|
|
.fdec_frn_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v),
|
|
.fdec_frn_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a),
|
|
.fdec_frn_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t),
|
|
.fdec_frn_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v),
|
|
.fdec_frn_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a),
|
|
.fdec_frn_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t),
|
|
.fdec_frn_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v),
|
|
.fdec_frn_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a),
|
|
.fdec_frn_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t),
|
|
.fdec_frn_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v),
|
|
.fdec_frn_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a),
|
|
.fdec_frn_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t),
|
|
.fdec_frn_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v),
|
|
.fdec_frn_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a),
|
|
.fdec_frn_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t),
|
|
|
|
.fdec_frn_iu5_i1_vld(fdec_frn_iu5_i1_vld),
|
|
.fdec_frn_iu5_i1_ucode(fdec_frn_iu5_i1_ucode),
|
|
.fdec_frn_iu5_i1_fuse_nop(fdec_frn_iu5_i1_fuse_nop),
|
|
.fdec_frn_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq),
|
|
.fdec_frn_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq),
|
|
.fdec_frn_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0),
|
|
.fdec_frn_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1),
|
|
.fdec_frn_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0),
|
|
.fdec_frn_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1),
|
|
.fdec_frn_iu5_i1_valop(fdec_frn_iu5_i1_valop),
|
|
.fdec_frn_iu5_i1_ord(fdec_frn_iu5_i1_ord),
|
|
.fdec_frn_iu5_i1_cord(fdec_frn_iu5_i1_cord),
|
|
.fdec_frn_iu5_i1_error(fdec_frn_iu5_i1_error),
|
|
.fdec_frn_iu5_i1_btb_entry(fdec_frn_iu5_i1_btb_entry),
|
|
.fdec_frn_iu5_i1_btb_hist(fdec_frn_iu5_i1_btb_hist),
|
|
.fdec_frn_iu5_i1_bta_val(fdec_frn_iu5_i1_bta_val),
|
|
.fdec_frn_iu5_i1_fusion(fdec_frn_iu5_i1_fusion),
|
|
.fdec_frn_iu5_i1_spec(fdec_frn_iu5_i1_spec),
|
|
.fdec_frn_iu5_i1_type_fp(fdec_frn_iu5_i1_type_fp),
|
|
.fdec_frn_iu5_i1_type_ap(fdec_frn_iu5_i1_type_ap),
|
|
.fdec_frn_iu5_i1_type_spv(fdec_frn_iu5_i1_type_spv),
|
|
.fdec_frn_iu5_i1_type_st(fdec_frn_iu5_i1_type_st),
|
|
.fdec_frn_iu5_i1_async_block(fdec_frn_iu5_i1_async_block),
|
|
.fdec_frn_iu5_i1_np1_flush(fdec_frn_iu5_i1_np1_flush),
|
|
.fdec_frn_iu5_i1_core_block(fdec_frn_iu5_i1_core_block),
|
|
.fdec_frn_iu5_i1_isram(fdec_frn_iu5_i1_isram),
|
|
.fdec_frn_iu5_i1_isload(fdec_frn_iu5_i1_isload),
|
|
.fdec_frn_iu5_i1_isstore(fdec_frn_iu5_i1_isstore),
|
|
.fdec_frn_iu5_i1_instr(fdec_frn_iu5_i1_instr),
|
|
.fdec_frn_iu5_i1_ifar(fdec_frn_iu5_i1_ifar),
|
|
.fdec_frn_iu5_i1_bta(fdec_frn_iu5_i1_bta),
|
|
.fdec_frn_iu5_i1_br_pred(fdec_frn_iu5_i1_br_pred),
|
|
.fdec_frn_iu5_i1_bh_update(fdec_frn_iu5_i1_bh_update),
|
|
.fdec_frn_iu5_i1_bh0_hist(fdec_frn_iu5_i1_bh0_hist),
|
|
.fdec_frn_iu5_i1_bh1_hist(fdec_frn_iu5_i1_bh1_hist),
|
|
.fdec_frn_iu5_i1_bh2_hist(fdec_frn_iu5_i1_bh2_hist),
|
|
.fdec_frn_iu5_i1_gshare(fdec_frn_iu5_i1_gshare),
|
|
.fdec_frn_iu5_i1_ls_ptr(fdec_frn_iu5_i1_ls_ptr),
|
|
.fdec_frn_iu5_i1_match(fdec_frn_iu5_i1_match),
|
|
.fdec_frn_iu5_i1_ilat(fdec_frn_iu5_i1_ilat),
|
|
.fdec_frn_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v),
|
|
.fdec_frn_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t),
|
|
.fdec_frn_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a),
|
|
.fdec_frn_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v),
|
|
.fdec_frn_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a),
|
|
.fdec_frn_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t),
|
|
.fdec_frn_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v),
|
|
.fdec_frn_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a),
|
|
.fdec_frn_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t),
|
|
.fdec_frn_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v),
|
|
.fdec_frn_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a),
|
|
.fdec_frn_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t),
|
|
.fdec_frn_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v),
|
|
.fdec_frn_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a),
|
|
.fdec_frn_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t),
|
|
.fdec_frn_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v),
|
|
.fdec_frn_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a),
|
|
.fdec_frn_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t),
|
|
|
|
//-----------------------------
|
|
// SPR values
|
|
//-----------------------------
|
|
.spr_high_pri_mask(spr_high_pri_mask),
|
|
.spr_cpcr_we(spr_cpcr_we),
|
|
.spr_cpcr3_cp_cnt(spr_cpcr3_cp_cnt),
|
|
.spr_cpcr5_cp_cnt(spr_cpcr5_cp_cnt),
|
|
.spr_single_issue(spr_single_issue),
|
|
|
|
//-----------------------------
|
|
// Stall to decode
|
|
//-----------------------------
|
|
.frn_fdec_iu5_stall(frn_fdec_iu5_stall),
|
|
.au_iu_iu5_stall(au_iu_iu5_stall),
|
|
|
|
//-----------------------------
|
|
// Stall from dispatch
|
|
//-----------------------------
|
|
.fdis_frn_iu6_stall(fdis_frn_iu6_stall),
|
|
|
|
//----------------------------
|
|
// Completion Interface
|
|
//----------------------------
|
|
.cp_rn_empty(cp_rn_empty),
|
|
.cp_rn_i0_v(cp_rn_i0_v),
|
|
.cp_rn_i0_itag(cp_rn_i0_itag),
|
|
.cp_rn_i0_t1_v(cp_rn_i0_t1_v),
|
|
.cp_rn_i0_t1_t(cp_rn_i0_t1_t),
|
|
.cp_rn_i0_t1_p(cp_rn_i0_t1_p),
|
|
.cp_rn_i0_t1_a(cp_rn_i0_t1_a),
|
|
.cp_rn_i0_t2_v(cp_rn_i0_t2_v),
|
|
.cp_rn_i0_t2_t(cp_rn_i0_t2_t),
|
|
.cp_rn_i0_t2_p(cp_rn_i0_t2_p),
|
|
.cp_rn_i0_t2_a(cp_rn_i0_t2_a),
|
|
.cp_rn_i0_t3_v(cp_rn_i0_t3_v),
|
|
.cp_rn_i0_t3_t(cp_rn_i0_t3_t),
|
|
.cp_rn_i0_t3_p(cp_rn_i0_t3_p),
|
|
.cp_rn_i0_t3_a(cp_rn_i0_t3_a),
|
|
|
|
.cp_rn_i1_v(cp_rn_i1_v),
|
|
.cp_rn_i1_itag(cp_rn_i1_itag),
|
|
.cp_rn_i1_t1_v(cp_rn_i1_t1_v),
|
|
.cp_rn_i1_t1_t(cp_rn_i1_t1_t),
|
|
.cp_rn_i1_t1_p(cp_rn_i1_t1_p),
|
|
.cp_rn_i1_t1_a(cp_rn_i1_t1_a),
|
|
.cp_rn_i1_t2_v(cp_rn_i1_t2_v),
|
|
.cp_rn_i1_t2_t(cp_rn_i1_t2_t),
|
|
.cp_rn_i1_t2_p(cp_rn_i1_t2_p),
|
|
.cp_rn_i1_t2_a(cp_rn_i1_t2_a),
|
|
.cp_rn_i1_t3_v(cp_rn_i1_t3_v),
|
|
.cp_rn_i1_t3_t(cp_rn_i1_t3_t),
|
|
.cp_rn_i1_t3_p(cp_rn_i1_t3_p),
|
|
.cp_rn_i1_t3_a(cp_rn_i1_t3_a),
|
|
|
|
.cp_flush(cp_flush),
|
|
.cp_flush_into_uc(cp_flush_into_uc),
|
|
.br_iu_redirect(br_iu_redirect),
|
|
.cp_rn_uc_credit_free(cp_rn_uc_credit_free),
|
|
|
|
//----------------------------------------------------------------
|
|
// AXU Interface
|
|
//----------------------------------------------------------------
|
|
.iu_au_iu5_send_ok(iu_au_iu5_send_ok),
|
|
.iu_au_iu5_next_itag_i0(iu_au_iu5_next_itag_i0),
|
|
.iu_au_iu5_next_itag_i1(iu_au_iu5_next_itag_i1),
|
|
.au_iu_iu5_axu0_send_ok(au_iu_iu5_axu0_send_ok),
|
|
.au_iu_iu5_axu1_send_ok(au_iu_iu5_axu1_send_ok),
|
|
|
|
.au_iu_iu5_i0_t1_p(au_iu_iu5_i0_t1_p),
|
|
.au_iu_iu5_i0_t2_p(au_iu_iu5_i0_t2_p),
|
|
.au_iu_iu5_i0_t3_p(au_iu_iu5_i0_t3_p),
|
|
.au_iu_iu5_i0_s1_p(au_iu_iu5_i0_s1_p),
|
|
.au_iu_iu5_i0_s2_p(au_iu_iu5_i0_s2_p),
|
|
.au_iu_iu5_i0_s3_p(au_iu_iu5_i0_s3_p),
|
|
|
|
.au_iu_iu5_i0_s1_itag(au_iu_iu5_i0_s1_itag),
|
|
.au_iu_iu5_i0_s2_itag(au_iu_iu5_i0_s2_itag),
|
|
.au_iu_iu5_i0_s3_itag(au_iu_iu5_i0_s3_itag),
|
|
|
|
.au_iu_iu5_i1_t1_p(au_iu_iu5_i1_t1_p),
|
|
.au_iu_iu5_i1_t2_p(au_iu_iu5_i1_t2_p),
|
|
.au_iu_iu5_i1_t3_p(au_iu_iu5_i1_t3_p),
|
|
.au_iu_iu5_i1_s1_p(au_iu_iu5_i1_s1_p),
|
|
.au_iu_iu5_i1_s2_p(au_iu_iu5_i1_s2_p),
|
|
.au_iu_iu5_i1_s3_p(au_iu_iu5_i1_s3_p),
|
|
|
|
.au_iu_iu5_i1_s1_dep_hit(au_iu_iu5_i1_s1_dep_hit),
|
|
.au_iu_iu5_i1_s2_dep_hit(au_iu_iu5_i1_s2_dep_hit),
|
|
.au_iu_iu5_i1_s3_dep_hit(au_iu_iu5_i1_s3_dep_hit),
|
|
|
|
.au_iu_iu5_i1_s1_itag(au_iu_iu5_i1_s1_itag),
|
|
.au_iu_iu5_i1_s2_itag(au_iu_iu5_i1_s2_itag),
|
|
.au_iu_iu5_i1_s3_itag(au_iu_iu5_i1_s3_itag),
|
|
|
|
//----------------------------------------------------------------
|
|
// Interface to reservation station - Completion is snooping also
|
|
//----------------------------------------------------------------
|
|
.frn_fdis_iu6_i0_vld(frn_fdis_iu6_i0_vld),
|
|
.frn_fdis_iu6_i0_itag(frn_fdis_iu6_i0_itag),
|
|
.frn_fdis_iu6_i0_ucode(frn_fdis_iu6_i0_ucode),
|
|
.frn_fdis_iu6_i0_ucode_cnt(frn_fdis_iu6_i0_ucode_cnt),
|
|
.frn_fdis_iu6_i0_2ucode(frn_fdis_iu6_i0_2ucode),
|
|
.frn_fdis_iu6_i0_fuse_nop(frn_fdis_iu6_i0_fuse_nop),
|
|
.frn_fdis_iu6_i0_rte_lq(frn_fdis_iu6_i0_rte_lq),
|
|
.frn_fdis_iu6_i0_rte_sq(frn_fdis_iu6_i0_rte_sq),
|
|
.frn_fdis_iu6_i0_rte_fx0(frn_fdis_iu6_i0_rte_fx0),
|
|
.frn_fdis_iu6_i0_rte_fx1(frn_fdis_iu6_i0_rte_fx1),
|
|
.frn_fdis_iu6_i0_rte_axu0(frn_fdis_iu6_i0_rte_axu0),
|
|
.frn_fdis_iu6_i0_rte_axu1(frn_fdis_iu6_i0_rte_axu1),
|
|
.frn_fdis_iu6_i0_valop(frn_fdis_iu6_i0_valop),
|
|
.frn_fdis_iu6_i0_ord(frn_fdis_iu6_i0_ord),
|
|
.frn_fdis_iu6_i0_cord(frn_fdis_iu6_i0_cord),
|
|
.frn_fdis_iu6_i0_error(frn_fdis_iu6_i0_error),
|
|
.frn_fdis_iu6_i0_btb_entry(frn_fdis_iu6_i0_btb_entry),
|
|
.frn_fdis_iu6_i0_btb_hist(frn_fdis_iu6_i0_btb_hist),
|
|
.frn_fdis_iu6_i0_bta_val(frn_fdis_iu6_i0_bta_val),
|
|
.frn_fdis_iu6_i0_fusion(frn_fdis_iu6_i0_fusion),
|
|
.frn_fdis_iu6_i0_spec(frn_fdis_iu6_i0_spec),
|
|
.frn_fdis_iu6_i0_type_fp(frn_fdis_iu6_i0_type_fp),
|
|
.frn_fdis_iu6_i0_type_ap(frn_fdis_iu6_i0_type_ap),
|
|
.frn_fdis_iu6_i0_type_spv(frn_fdis_iu6_i0_type_spv),
|
|
.frn_fdis_iu6_i0_type_st(frn_fdis_iu6_i0_type_st),
|
|
.frn_fdis_iu6_i0_async_block(frn_fdis_iu6_i0_async_block),
|
|
.frn_fdis_iu6_i0_np1_flush(frn_fdis_iu6_i0_np1_flush),
|
|
.frn_fdis_iu6_i0_core_block(frn_fdis_iu6_i0_core_block),
|
|
.frn_fdis_iu6_i0_isram(frn_fdis_iu6_i0_isram),
|
|
.frn_fdis_iu6_i0_isload(frn_fdis_iu6_i0_isload),
|
|
.frn_fdis_iu6_i0_isstore(frn_fdis_iu6_i0_isstore),
|
|
.frn_fdis_iu6_i0_instr(frn_fdis_iu6_i0_instr),
|
|
.frn_fdis_iu6_i0_ifar(frn_fdis_iu6_i0_ifar),
|
|
.frn_fdis_iu6_i0_bta(frn_fdis_iu6_i0_bta),
|
|
.frn_fdis_iu6_i0_br_pred(frn_fdis_iu6_i0_br_pred),
|
|
.frn_fdis_iu6_i0_bh_update(frn_fdis_iu6_i0_bh_update),
|
|
.frn_fdis_iu6_i0_bh0_hist(frn_fdis_iu6_i0_bh0_hist),
|
|
.frn_fdis_iu6_i0_bh1_hist(frn_fdis_iu6_i0_bh1_hist),
|
|
.frn_fdis_iu6_i0_bh2_hist(frn_fdis_iu6_i0_bh2_hist),
|
|
.frn_fdis_iu6_i0_gshare(frn_fdis_iu6_i0_gshare),
|
|
.frn_fdis_iu6_i0_ls_ptr(frn_fdis_iu6_i0_ls_ptr),
|
|
.frn_fdis_iu6_i0_match(frn_fdis_iu6_i0_match),
|
|
.frn_fdis_iu6_i0_ilat(frn_fdis_iu6_i0_ilat),
|
|
.frn_fdis_iu6_i0_t1_v(frn_fdis_iu6_i0_t1_v),
|
|
.frn_fdis_iu6_i0_t1_t(frn_fdis_iu6_i0_t1_t),
|
|
.frn_fdis_iu6_i0_t1_a(frn_fdis_iu6_i0_t1_a),
|
|
.frn_fdis_iu6_i0_t1_p(frn_fdis_iu6_i0_t1_p),
|
|
.frn_fdis_iu6_i0_t2_v(frn_fdis_iu6_i0_t2_v),
|
|
.frn_fdis_iu6_i0_t2_a(frn_fdis_iu6_i0_t2_a),
|
|
.frn_fdis_iu6_i0_t2_p(frn_fdis_iu6_i0_t2_p),
|
|
.frn_fdis_iu6_i0_t2_t(frn_fdis_iu6_i0_t2_t),
|
|
.frn_fdis_iu6_i0_t3_v(frn_fdis_iu6_i0_t3_v),
|
|
.frn_fdis_iu6_i0_t3_a(frn_fdis_iu6_i0_t3_a),
|
|
.frn_fdis_iu6_i0_t3_p(frn_fdis_iu6_i0_t3_p),
|
|
.frn_fdis_iu6_i0_t3_t(frn_fdis_iu6_i0_t3_t),
|
|
.frn_fdis_iu6_i0_s1_v(frn_fdis_iu6_i0_s1_v),
|
|
.frn_fdis_iu6_i0_s1_a(frn_fdis_iu6_i0_s1_a),
|
|
.frn_fdis_iu6_i0_s1_p(frn_fdis_iu6_i0_s1_p),
|
|
.frn_fdis_iu6_i0_s1_itag(frn_fdis_iu6_i0_s1_itag),
|
|
.frn_fdis_iu6_i0_s1_t(frn_fdis_iu6_i0_s1_t),
|
|
.frn_fdis_iu6_i0_s2_v(frn_fdis_iu6_i0_s2_v),
|
|
.frn_fdis_iu6_i0_s2_a(frn_fdis_iu6_i0_s2_a),
|
|
.frn_fdis_iu6_i0_s2_p(frn_fdis_iu6_i0_s2_p),
|
|
.frn_fdis_iu6_i0_s2_itag(frn_fdis_iu6_i0_s2_itag),
|
|
.frn_fdis_iu6_i0_s2_t(frn_fdis_iu6_i0_s2_t),
|
|
.frn_fdis_iu6_i0_s3_v(frn_fdis_iu6_i0_s3_v),
|
|
.frn_fdis_iu6_i0_s3_a(frn_fdis_iu6_i0_s3_a),
|
|
.frn_fdis_iu6_i0_s3_p(frn_fdis_iu6_i0_s3_p),
|
|
.frn_fdis_iu6_i0_s3_itag(frn_fdis_iu6_i0_s3_itag),
|
|
.frn_fdis_iu6_i0_s3_t(frn_fdis_iu6_i0_s3_t),
|
|
|
|
.frn_fdis_iu6_i1_vld(frn_fdis_iu6_i1_vld),
|
|
.frn_fdis_iu6_i1_itag(frn_fdis_iu6_i1_itag),
|
|
.frn_fdis_iu6_i1_ucode(frn_fdis_iu6_i1_ucode),
|
|
.frn_fdis_iu6_i1_ucode_cnt(frn_fdis_iu6_i1_ucode_cnt),
|
|
.frn_fdis_iu6_i1_fuse_nop(frn_fdis_iu6_i1_fuse_nop),
|
|
.frn_fdis_iu6_i1_rte_lq(frn_fdis_iu6_i1_rte_lq),
|
|
.frn_fdis_iu6_i1_rte_sq(frn_fdis_iu6_i1_rte_sq),
|
|
.frn_fdis_iu6_i1_rte_fx0(frn_fdis_iu6_i1_rte_fx0),
|
|
.frn_fdis_iu6_i1_rte_fx1(frn_fdis_iu6_i1_rte_fx1),
|
|
.frn_fdis_iu6_i1_rte_axu0(frn_fdis_iu6_i1_rte_axu0),
|
|
.frn_fdis_iu6_i1_rte_axu1(frn_fdis_iu6_i1_rte_axu1),
|
|
.frn_fdis_iu6_i1_valop(frn_fdis_iu6_i1_valop),
|
|
.frn_fdis_iu6_i1_ord(frn_fdis_iu6_i1_ord),
|
|
.frn_fdis_iu6_i1_cord(frn_fdis_iu6_i1_cord),
|
|
.frn_fdis_iu6_i1_error(frn_fdis_iu6_i1_error),
|
|
.frn_fdis_iu6_i1_btb_entry(frn_fdis_iu6_i1_btb_entry),
|
|
.frn_fdis_iu6_i1_btb_hist(frn_fdis_iu6_i1_btb_hist),
|
|
.frn_fdis_iu6_i1_bta_val(frn_fdis_iu6_i1_bta_val),
|
|
.frn_fdis_iu6_i1_fusion(frn_fdis_iu6_i1_fusion),
|
|
.frn_fdis_iu6_i1_spec(frn_fdis_iu6_i1_spec),
|
|
.frn_fdis_iu6_i1_type_fp(frn_fdis_iu6_i1_type_fp),
|
|
.frn_fdis_iu6_i1_type_ap(frn_fdis_iu6_i1_type_ap),
|
|
.frn_fdis_iu6_i1_type_spv(frn_fdis_iu6_i1_type_spv),
|
|
.frn_fdis_iu6_i1_type_st(frn_fdis_iu6_i1_type_st),
|
|
.frn_fdis_iu6_i1_async_block(frn_fdis_iu6_i1_async_block),
|
|
.frn_fdis_iu6_i1_np1_flush(frn_fdis_iu6_i1_np1_flush),
|
|
.frn_fdis_iu6_i1_core_block(frn_fdis_iu6_i1_core_block),
|
|
.frn_fdis_iu6_i1_isram(frn_fdis_iu6_i1_isram),
|
|
.frn_fdis_iu6_i1_isload(frn_fdis_iu6_i1_isload),
|
|
.frn_fdis_iu6_i1_isstore(frn_fdis_iu6_i1_isstore),
|
|
.frn_fdis_iu6_i1_instr(frn_fdis_iu6_i1_instr),
|
|
.frn_fdis_iu6_i1_ifar(frn_fdis_iu6_i1_ifar),
|
|
.frn_fdis_iu6_i1_bta(frn_fdis_iu6_i1_bta),
|
|
.frn_fdis_iu6_i1_br_pred(frn_fdis_iu6_i1_br_pred),
|
|
.frn_fdis_iu6_i1_bh_update(frn_fdis_iu6_i1_bh_update),
|
|
.frn_fdis_iu6_i1_bh0_hist(frn_fdis_iu6_i1_bh0_hist),
|
|
.frn_fdis_iu6_i1_bh1_hist(frn_fdis_iu6_i1_bh1_hist),
|
|
.frn_fdis_iu6_i1_bh2_hist(frn_fdis_iu6_i1_bh2_hist),
|
|
.frn_fdis_iu6_i1_gshare(frn_fdis_iu6_i1_gshare),
|
|
.frn_fdis_iu6_i1_ls_ptr(frn_fdis_iu6_i1_ls_ptr),
|
|
.frn_fdis_iu6_i1_match(frn_fdis_iu6_i1_match),
|
|
.frn_fdis_iu6_i1_ilat(frn_fdis_iu6_i1_ilat),
|
|
.frn_fdis_iu6_i1_t1_v(frn_fdis_iu6_i1_t1_v),
|
|
.frn_fdis_iu6_i1_t1_t(frn_fdis_iu6_i1_t1_t),
|
|
.frn_fdis_iu6_i1_t1_a(frn_fdis_iu6_i1_t1_a),
|
|
.frn_fdis_iu6_i1_t1_p(frn_fdis_iu6_i1_t1_p),
|
|
.frn_fdis_iu6_i1_t2_v(frn_fdis_iu6_i1_t2_v),
|
|
.frn_fdis_iu6_i1_t2_a(frn_fdis_iu6_i1_t2_a),
|
|
.frn_fdis_iu6_i1_t2_p(frn_fdis_iu6_i1_t2_p),
|
|
.frn_fdis_iu6_i1_t2_t(frn_fdis_iu6_i1_t2_t),
|
|
.frn_fdis_iu6_i1_t3_v(frn_fdis_iu6_i1_t3_v),
|
|
.frn_fdis_iu6_i1_t3_a(frn_fdis_iu6_i1_t3_a),
|
|
.frn_fdis_iu6_i1_t3_p(frn_fdis_iu6_i1_t3_p),
|
|
.frn_fdis_iu6_i1_t3_t(frn_fdis_iu6_i1_t3_t),
|
|
.frn_fdis_iu6_i1_s1_v(frn_fdis_iu6_i1_s1_v),
|
|
.frn_fdis_iu6_i1_s1_a(frn_fdis_iu6_i1_s1_a),
|
|
.frn_fdis_iu6_i1_s1_p(frn_fdis_iu6_i1_s1_p),
|
|
.frn_fdis_iu6_i1_s1_itag(frn_fdis_iu6_i1_s1_itag),
|
|
.frn_fdis_iu6_i1_s1_t(frn_fdis_iu6_i1_s1_t),
|
|
.frn_fdis_iu6_i1_s1_dep_hit(frn_fdis_iu6_i1_s1_dep_hit),
|
|
.frn_fdis_iu6_i1_s2_v(frn_fdis_iu6_i1_s2_v),
|
|
.frn_fdis_iu6_i1_s2_a(frn_fdis_iu6_i1_s2_a),
|
|
.frn_fdis_iu6_i1_s2_p(frn_fdis_iu6_i1_s2_p),
|
|
.frn_fdis_iu6_i1_s2_itag(frn_fdis_iu6_i1_s2_itag),
|
|
.frn_fdis_iu6_i1_s2_t(frn_fdis_iu6_i1_s2_t),
|
|
.frn_fdis_iu6_i1_s2_dep_hit(frn_fdis_iu6_i1_s2_dep_hit),
|
|
.frn_fdis_iu6_i1_s3_v(frn_fdis_iu6_i1_s3_v),
|
|
.frn_fdis_iu6_i1_s3_a(frn_fdis_iu6_i1_s3_a),
|
|
.frn_fdis_iu6_i1_s3_p(frn_fdis_iu6_i1_s3_p),
|
|
.frn_fdis_iu6_i1_s3_itag(frn_fdis_iu6_i1_s3_itag),
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|
.frn_fdis_iu6_i1_s3_t(frn_fdis_iu6_i1_s3_t),
|
|
.frn_fdis_iu6_i1_s3_dep_hit(frn_fdis_iu6_i1_s3_dep_hit)
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|
|
|
);
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iuq_axu_fu_rn #(.FPR_POOL(`GPR_POOL), .FPR_UCODE_POOL(4), .FPSCR_POOL_ENC(5)) axu_rn0(
|
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.vdd(vdd), // inout power_logic;
|
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.gnd(gnd), // inout power_logic;
|
|
.nclk(nclk), // in clk_logic;
|
|
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), // in std_ulogic; acts as reset for non-ibm types
|
|
.pc_iu_sg_2(pc_iu_sg_2), // in std_ulogic;
|
|
.clkoff_b(clkoff_b), // in std_ulogic; todo
|
|
.act_dis(act_dis), // in std_ulogic; todo
|
|
.tc_ac_ccflush_dc(tc_ac_ccflush_dc), // in std_ulogic; todo
|
|
.d_mode(d_mode), // in std_ulogic;
|
|
.delay_lclkr(delay_lclkr), // in std_ulogic;
|
|
.mpw1_b(mpw1_b), // in std_ulogic;
|
|
.mpw2_b(mpw2_b), // in std_ulogic;
|
|
.func_scan_in(func_scan_in[1]), // in std_ulogic; todo: hookup
|
|
.func_scan_out(func_scan_out[1]), // out std_ulogic;
|
|
|
|
.iu_au_iu5_i0_vld(fdec_frn_iu5_i0_vld),
|
|
.iu_au_iu5_i0_ucode(fdec_frn_iu5_i0_ucode),
|
|
.iu_au_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq),
|
|
.iu_au_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq),
|
|
.iu_au_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0),
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|
.iu_au_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1),
|
|
.iu_au_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0),
|
|
.iu_au_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1),
|
|
.iu_au_iu5_i0_ord(fdec_frn_iu5_i0_ord),
|
|
.iu_au_iu5_i0_cord(fdec_frn_iu5_i0_cord),
|
|
.iu_au_iu5_i0_instr(fdec_frn_iu5_i0_instr),
|
|
.iu_au_iu5_i0_ifar(fdec_frn_iu5_i0_ifar),
|
|
.iu_au_iu5_i0_gshare(fdec_frn_iu5_i0_gshare[0:9]),
|
|
.iu_au_iu5_i0_ilat(fdec_frn_iu5_i0_ilat),
|
|
.iu_au_iu5_i0_isload(fdec_frn_iu5_i0_isload),
|
|
.iu_au_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v),
|
|
.iu_au_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t),
|
|
.iu_au_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a),
|
|
.iu_au_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v),
|
|
.iu_au_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t),
|
|
.iu_au_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a),
|
|
.iu_au_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v),
|
|
.iu_au_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t),
|
|
.iu_au_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a),
|
|
.iu_au_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v),
|
|
.iu_au_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t),
|
|
.iu_au_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a),
|
|
.iu_au_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v),
|
|
.iu_au_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t),
|
|
.iu_au_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a),
|
|
.iu_au_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v),
|
|
.iu_au_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t),
|
|
.iu_au_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a),
|
|
.iu_au_iu5_i1_vld(fdec_frn_iu5_i1_vld),
|
|
.iu_au_iu5_i1_ucode(fdec_frn_iu5_i1_ucode),
|
|
.iu_au_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq),
|
|
.iu_au_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq),
|
|
.iu_au_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0),
|
|
.iu_au_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1),
|
|
.iu_au_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0),
|
|
.iu_au_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1),
|
|
.iu_au_iu5_i1_ord(fdec_frn_iu5_i1_ord),
|
|
.iu_au_iu5_i1_cord(fdec_frn_iu5_i1_cord),
|
|
.iu_au_iu5_i1_instr(fdec_frn_iu5_i1_instr),
|
|
.iu_au_iu5_i1_ifar(fdec_frn_iu5_i1_ifar),
|
|
.iu_au_iu5_i1_gshare(fdec_frn_iu5_i1_gshare[0:9]),
|
|
.iu_au_iu5_i1_ilat(fdec_frn_iu5_i1_ilat),
|
|
.iu_au_iu5_i1_isload(fdec_frn_iu5_i1_isload),
|
|
.iu_au_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v),
|
|
.iu_au_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t),
|
|
.iu_au_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a),
|
|
.iu_au_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v),
|
|
.iu_au_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t),
|
|
.iu_au_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a),
|
|
.iu_au_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v),
|
|
.iu_au_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t),
|
|
.iu_au_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a),
|
|
.iu_au_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v),
|
|
.iu_au_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t),
|
|
.iu_au_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a),
|
|
.iu_au_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v),
|
|
.iu_au_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t),
|
|
.iu_au_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a),
|
|
.iu_au_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v),
|
|
.iu_au_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t),
|
|
.iu_au_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a),
|
|
|
|
.spr_single_issue(1'b0), // in std_ulogic;
|
|
|
|
.au_iu_iu5_stall(au_iu_iu5_stall), // out std_ulogic;
|
|
|
|
.cp_rn_i0_axu_exception_val(cp_rn_i0_axu_exception_val),
|
|
.cp_rn_i0_axu_exception(cp_rn_i0_axu_exception),
|
|
.cp_rn_i0_itag(cp_rn_i0_itag),
|
|
.cp_rn_i0_t1_v(cp_rn_i0_t1_v), // in std_ulogic;
|
|
.cp_rn_i0_t1_t(cp_rn_i0_t1_t), // in std_ulogic;
|
|
.cp_rn_i0_t1_p(cp_rn_i0_t1_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i0_t1_a(cp_rn_i0_t1_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i0_t2_v(cp_rn_i0_t2_v), // in std_ulogic;
|
|
.cp_rn_i0_t2_t(cp_rn_i0_t2_t), // in std_ulogic_vector(0 to 2);
|
|
.cp_rn_i0_t2_p(cp_rn_i0_t2_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i0_t2_a(cp_rn_i0_t2_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i0_t3_v(cp_rn_i0_t3_v), // in std_ulogic;
|
|
.cp_rn_i0_t3_t(cp_rn_i0_t3_t), // in std_ulogic_vector(0 to 2);
|
|
.cp_rn_i0_t3_p(cp_rn_i0_t3_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i0_t3_a(cp_rn_i0_t3_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
|
|
.cp_rn_i1_axu_exception_val(cp_rn_i1_axu_exception_val),
|
|
.cp_rn_i1_axu_exception(cp_rn_i1_axu_exception),
|
|
.cp_rn_i1_itag(cp_rn_i1_itag),
|
|
.cp_rn_i1_t1_v(cp_rn_i1_t1_v), // in std_ulogic;
|
|
.cp_rn_i1_t1_t(cp_rn_i1_t1_t), // in std_ulogic;
|
|
.cp_rn_i1_t1_p(cp_rn_i1_t1_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i1_t1_a(cp_rn_i1_t1_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i1_t2_v(cp_rn_i1_t2_v), // in std_ulogic;
|
|
.cp_rn_i1_t2_t(cp_rn_i1_t2_t), // in std_ulogic_vector(0 to 2);
|
|
.cp_rn_i1_t2_p(cp_rn_i1_t2_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i1_t2_a(cp_rn_i1_t2_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i1_t3_v(cp_rn_i1_t3_v), // in std_ulogic;
|
|
.cp_rn_i1_t3_t(cp_rn_i1_t3_t), // in std_ulogic_vector(0 to 2);
|
|
.cp_rn_i1_t3_p(cp_rn_i1_t3_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
.cp_rn_i1_t3_a(cp_rn_i1_t3_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1);
|
|
|
|
.cp_flush(cp_flush), // in std_ulogic;
|
|
.br_iu_redirect(br_iu_redirect),
|
|
.iu_au_iu5_send_ok(iu_au_iu5_send_ok),
|
|
.iu_au_iu5_next_itag_i0(iu_au_iu5_next_itag_i0),
|
|
.iu_au_iu5_next_itag_i1(iu_au_iu5_next_itag_i1),
|
|
.au_iu_iu5_axu0_send_ok(au_iu_iu5_axu0_send_ok),
|
|
.au_iu_iu5_axu1_send_ok(au_iu_iu5_axu1_send_ok),
|
|
.au_iu_iu5_i0_t1_p(au_iu_iu5_i0_t1_p),
|
|
.au_iu_iu5_i0_t2_p(au_iu_iu5_i0_t2_p),
|
|
.au_iu_iu5_i0_t3_p(au_iu_iu5_i0_t3_p),
|
|
.au_iu_iu5_i0_s1_p(au_iu_iu5_i0_s1_p),
|
|
.au_iu_iu5_i0_s2_p(au_iu_iu5_i0_s2_p),
|
|
.au_iu_iu5_i0_s3_p(au_iu_iu5_i0_s3_p),
|
|
.au_iu_iu5_i0_s1_itag(au_iu_iu5_i0_s1_itag),
|
|
.au_iu_iu5_i0_s2_itag(au_iu_iu5_i0_s2_itag),
|
|
.au_iu_iu5_i0_s3_itag(au_iu_iu5_i0_s3_itag),
|
|
.au_iu_iu5_i1_t1_p(au_iu_iu5_i1_t1_p),
|
|
.au_iu_iu5_i1_t2_p(au_iu_iu5_i1_t2_p),
|
|
.au_iu_iu5_i1_t3_p(au_iu_iu5_i1_t3_p),
|
|
.au_iu_iu5_i1_s1_p(au_iu_iu5_i1_s1_p),
|
|
.au_iu_iu5_i1_s2_p(au_iu_iu5_i1_s2_p),
|
|
.au_iu_iu5_i1_s3_p(au_iu_iu5_i1_s3_p),
|
|
.au_iu_iu5_i1_s1_dep_hit(au_iu_iu5_i1_s1_dep_hit),
|
|
.au_iu_iu5_i1_s2_dep_hit(au_iu_iu5_i1_s2_dep_hit),
|
|
.au_iu_iu5_i1_s3_dep_hit(au_iu_iu5_i1_s3_dep_hit),
|
|
.au_iu_iu5_i1_s1_itag(au_iu_iu5_i1_s1_itag),
|
|
.au_iu_iu5_i1_s2_itag(au_iu_iu5_i1_s2_itag),
|
|
.au_iu_iu5_i1_s3_itag(au_iu_iu5_i1_s3_itag)
|
|
);
|
|
|
|
endmodule
|