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345 lines
12 KiB
Verilog
345 lines
12 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//********************************************************************
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//*
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//* TITLE: Microcode Completion Buffer
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//*
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//* NAME: iuq_uc_cplbuffer.v
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//*
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//*********************************************************************
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`include "tri_a2o.vh"
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module iuq_uc_cplbuffer(
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vdd,
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gnd,
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nclk,
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pc_iu_func_sl_thold_0_b,
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pc_iu_sg_0,
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force_t,
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d_mode,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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scan_in,
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scan_out,
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cp_uc_credit_free,
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flush,
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flush_into_uc,
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new_command,
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flush_next,
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valid_l2,
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flush_current,
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buff_instr_in,
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cplbuffer_xer_act,
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wait_for_xer_l2,
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xu_iu_ucode_xer_l2,
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cplbuffer_full,
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oldest_instr,
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oldest_xer
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);
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inout vdd;
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inout gnd;
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(* pin_data="PIN_FUNCTION=/G_CLK/" *)
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input [0:`NCLK_WIDTH-1] nclk;
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input pc_iu_func_sl_thold_0_b;
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input pc_iu_sg_0;
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input force_t;
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input d_mode;
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input delay_lclkr;
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input mpw1_b;
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input mpw2_b;
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(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
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input scan_in;
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(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
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output scan_out;
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input cp_uc_credit_free;
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input flush;
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input flush_into_uc;
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input new_command;
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input flush_next;
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input valid_l2;
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input flush_current;
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input [0:31] buff_instr_in;
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input cplbuffer_xer_act;
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input wait_for_xer_l2;
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input [57:63] xu_iu_ucode_xer_l2;
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output cplbuffer_full;
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output reg [0:31] oldest_instr;
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output reg [57:63] oldest_xer;
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// iuq_uc_cplbuffer
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localparam [0:31] value_1 = 32'h00000001;
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localparam [0:31] value_2 = 32'h00000002;
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parameter buffer_width = 32;
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parameter buffer_depth = 8; // NOTE: If this changes, change cplbuffer_full logic
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parameter buffer_depth_log = 3;
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parameter xer_width = 7;
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parameter buffer_count_offset = 0;
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parameter buffer_offset = buffer_count_offset + buffer_depth_log + 1;
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parameter xer_offset = buffer_offset + buffer_depth * buffer_width;
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parameter read_ptr_offset = xer_offset + buffer_depth * xer_width;
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parameter write_ptr_offset = read_ptr_offset + buffer_depth_log;
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parameter new_command_offset = write_ptr_offset + buffer_depth_log;
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parameter scan_right = new_command_offset + 1 - 1;
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wire [0:buffer_depth_log] buffer_count_d;
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wire [0:buffer_depth_log] buffer_count_l2;
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reg [0:buffer_width-1] buffer_d[0:buffer_depth-1];
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wire [0:buffer_width-1] buffer_l2[0:buffer_depth-1];
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reg [57:63] xer_d[0:buffer_depth-1];
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wire [57:63] xer_l2[0:buffer_depth-1];
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wire [0:buffer_depth_log-1] read_ptr_d;
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wire [0:buffer_depth_log-1] read_ptr_l2;
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wire [0:buffer_depth_log-1] write_ptr_d;
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wire [0:buffer_depth_log-1] write_ptr_l2;
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wire new_command_d;
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wire new_command_l2;
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wire [0:buffer_depth_log-1] xer_write_ptr;
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wire [0:1] buffer_act;
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wire ptr_act;
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wire cplbuffer_full_int;
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wire tiup;
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// scan
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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assign tiup = 1'b1;
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assign new_command_d = new_command & (~(flush_next));
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assign buffer_count_d = (flush_into_uc == 1'b1) ? value_1[31-buffer_depth_log:31] :
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(flush == 1'b1) ? {(buffer_depth_log+1){1'b0}} : //cp_flush
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(new_command_l2 == 1'b0 & (flush_current & valid_l2) == 1'b1 & cp_uc_credit_free == 1'b1) ? buffer_count_l2 - value_2[31-buffer_depth_log:31] :
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(new_command_l2 == 1'b0 & (flush_current & valid_l2) == 1'b1 & cp_uc_credit_free == 1'b0) ? buffer_count_l2 - value_1[31-buffer_depth_log:31] :
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(new_command_l2 == 1'b0 & (flush_current & valid_l2) == 1'b0 & cp_uc_credit_free == 1'b1) ? buffer_count_l2 - value_1[31-buffer_depth_log:31] :
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(new_command_l2 == 1'b1 & (flush_current & valid_l2) == 1'b1 & cp_uc_credit_free == 1'b1) ? buffer_count_l2 - value_1[31-buffer_depth_log:31] :
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(new_command_l2 == 1'b1 & (flush_current & valid_l2) == 1'b0 & cp_uc_credit_free == 1'b0) ? buffer_count_l2 + value_1[31-buffer_depth_log:31] :
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buffer_count_l2;
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assign read_ptr_d = (cp_uc_credit_free == 1'b1) ? read_ptr_l2 + value_1[32-buffer_depth_log:31] :
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read_ptr_l2;
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assign write_ptr_d = (flush_into_uc == 1'b1) ? read_ptr_l2 + value_1[32-buffer_depth_log:31] :
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(flush == 1'b1) ? read_ptr_l2 :
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(new_command_l2 == 1'b1 & ((flush_current & valid_l2) == 1'b0)) ? write_ptr_l2 + value_1[32-buffer_depth_log:31] :
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(new_command_l2 == 1'b0 & ((flush_current & valid_l2) == 1'b1)) ? write_ptr_l2 - value_1[32-buffer_depth_log:31] :
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write_ptr_l2;
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generate
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begin : gen_buff
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genvar i;
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for (i = 0; i < buffer_depth; i = i + 1)
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begin : buff_loop
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wire [0:buffer_depth_log-1] index=i;
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always @*
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begin
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buffer_d[i] = (write_ptr_l2 == index) ? buff_instr_in :
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buffer_l2[i];
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xer_d[i] = (xer_write_ptr == index) ? xu_iu_ucode_xer_l2 :
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xer_l2[i];
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end
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end
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end
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endgenerate
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always @ (*)
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begin : read_mux
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//(* analysis_not_referenced="true" *)
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integer i;
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oldest_instr = 32'b0;
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oldest_xer = 7'b0;
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for (i = 0; i < buffer_depth; i = i + 1)
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begin : read_mux_loop
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if (read_ptr_l2 == i[buffer_depth_log-1:0])
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begin
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oldest_instr = buffer_l2[i];
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oldest_xer = xer_l2[i];
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end
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end
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end
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assign xer_write_ptr = (wait_for_xer_l2 == 1'b1) ? write_ptr_l2 - value_1[32-buffer_depth_log:31] : // when xer comes after new_command
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write_ptr_l2; // when xer valid with new_command
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assign cplbuffer_full_int = (buffer_count_l2[1:2] == 2'b11);
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assign cplbuffer_full = cplbuffer_full_int;
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assign buffer_act[0] = new_command_l2 & (~write_ptr_l2[0]);
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assign buffer_act[1] = new_command_l2 & write_ptr_l2[0];
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assign ptr_act = flush_into_uc | flush | new_command_l2 | cp_uc_credit_free | flush_current;
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//---------------------------------------------------------------------
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// Latches
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//---------------------------------------------------------------------
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tri_rlmreg_p #(.WIDTH(buffer_depth_log+1), .INIT(0)) buffer_count_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(ptr_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[buffer_count_offset:buffer_count_offset + (buffer_depth_log+1) - 1]),
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.scout(sov[buffer_count_offset:buffer_count_offset + (buffer_depth_log+1) - 1]),
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.din(buffer_count_d),
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.dout(buffer_count_l2)
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);
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generate
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begin
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genvar i;
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for (i = 0; i < buffer_depth; i = i + 1)
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begin : gen_b
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tri_rlmreg_p #(.WIDTH(buffer_width), .INIT(0)) buffer_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(buffer_act[i/(buffer_depth/2)]), // only clock half of buffers at a time
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[buffer_offset + i * buffer_width:buffer_offset + (i + 1) * buffer_width - 1]),
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.scout(sov[buffer_offset + i * buffer_width:buffer_offset + (i + 1) * buffer_width - 1]),
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.din(buffer_d[i]),
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.dout(buffer_l2[i])
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);
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tri_rlmreg_p #(.WIDTH(xer_width), .INIT(0)) xer_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(cplbuffer_xer_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[xer_offset + i * xer_width:xer_offset + (i + 1) * xer_width - 1]),
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.scout(sov[xer_offset + i * xer_width:xer_offset + (i + 1) * xer_width - 1]),
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.din(xer_d[i]),
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.dout(xer_l2[i])
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);
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end
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end
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endgenerate
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tri_rlmreg_p #(.WIDTH(buffer_depth_log), .INIT(0)) read_ptr_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(ptr_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[read_ptr_offset:read_ptr_offset + buffer_depth_log - 1]),
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.scout(sov[read_ptr_offset:read_ptr_offset + buffer_depth_log - 1]),
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.din(read_ptr_d),
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.dout(read_ptr_l2)
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);
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tri_rlmreg_p #(.WIDTH(buffer_depth_log), .INIT(0)) write_ptr_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(ptr_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[write_ptr_offset:write_ptr_offset + buffer_depth_log - 1]),
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.scout(sov[write_ptr_offset:write_ptr_offset + buffer_depth_log - 1]),
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.din(write_ptr_d),
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.dout(write_ptr_l2)
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);
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tri_rlmlatch_p #(.INIT(0)) new_command_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[new_command_offset]),
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.scout(sov[new_command_offset]),
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.din(new_command_d),
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.dout(new_command_l2)
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);
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//---------------------------------------------------------------------
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// Scan
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//---------------------------------------------------------------------
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assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
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assign scan_out = sov[0];
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endmodule
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