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182 lines
6.1 KiB
Verilog
182 lines
6.1 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// input phase is importent
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// (change X (B) by switching xor/xnor )
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module lq_agen_loca(
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x_b,
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y_b,
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sum_0,
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sum_1
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);
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input [0:7] x_b; // after xor
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input [0:7] y_b;
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output [0:7] sum_0;
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output [0:7] sum_1;
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wire [0:7] h01;
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wire [0:7] h01_b;
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wire [0:7] x;
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wire [0:7] y;
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wire [1:7] g01_b;
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wire [1:7] t01_b;
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wire [0:7] p01;
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wire [0:7] p01_b;
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wire [1:7] g08_b;
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wire [1:7] g08;
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wire [1:7] g04_b;
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wire [1:7] g02;
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wire [1:7] t02;
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wire [1:7] t04_b;
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wire [1:7] t08;
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wire [1:7] t08_b;
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//####################################################################
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//# inverter at top to drive to bit location
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//####################################################################
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//assign x[0:7] = (~x_b[0:7]); // maybe should be fat wire
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tri_inv #(.WIDTH(8)) x_0 (.y(x[0:7]), .a(x_b[0:7]));
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//assign y[0:7] = (~y_b[0:7]); // maybe should be fat wire
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tri_inv #(.WIDTH(8)) y_0 (.y(y[0:7]), .a(y_b[0:7]));
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//####################################################################
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//# funny way to make xor
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//####################################################################
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//assign g01_b[1:7] = (~(x[1:7] & y[1:7]));
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tri_nand2 #(.WIDTH(7)) g01_b_1 (.y(g01_b[1:7]), .a(x[1:7]), .b(y[1:7]));
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//assign t01_b[1:7] = (~(x[1:7] | y[1:7]));
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tri_nor2 #(.WIDTH(7)) t01_b_1 (.y(t01_b[1:7]), .a(x[1:7]), .b(y[1:7]));
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//assign p01_b[0:7] = (~(x[0:7] ^ y[0:7]));
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tri_xnor2 #(.WIDTH(8)) p01_b_0 (.y(p01_b[0:7]), .a(x[0:7]), .b(y[0:7]));
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//assign p01[0:7] = (~(p01_b[0:7]));
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tri_inv #(.WIDTH(8)) p01_0 (.y(p01[0:7]), .a(p01_b[0:7]));
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//assign h01[0:7] = (~p01_b[0:7]);
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tri_inv #(.WIDTH(8)) h01_0 (.y(h01[0:7]), .a(p01_b[0:7]));
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//assign h01_b[0:7] = (~p01[0:7]);
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tri_inv #(.WIDTH(8)) h01_b_0 (.y(h01_b[0:7]), .a(p01[0:7]));
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//####################################################################
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//# local carry
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//####################################################################
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//assign g02[1] = (~(g01_b[1] & (t01_b[1] | g01_b[2])));
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tri_oai21 #(.WIDTH(6)) g02_1 (.y(g02[1:6]), .a0(t01_b[1:6]), .a1(g01_b[2:7]), .b0(g01_b[1:6]));
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//assign g02[7] = (~(g01_b[7]));
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tri_inv g02_7 (.y(g02[7]), .a(g01_b[7]));
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//assign t02[1] = (~(t01_b[1] | t01_b[2]));
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tri_nor2 #(.WIDTH(5)) t02_1 (.y(t02[1:5]), .a(t01_b[1:5]), .b(t01_b[2:6]));
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//assign t02[6] = (~(g01_b[6] & (t01_b[6] | t01_b[7]))); //final--
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tri_oai21 t02_6 (.y(t02[6]), .a0(t01_b[6]), .a1(t01_b[7]), .b0(g01_b[6]));
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//assign t02[7] = (~(t01_b[7]));
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tri_inv t02_7 (.y(t02[7]), .a(t01_b[7]));
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//assign g04_b[1] = (~(g02[1] | (t02[1] & g02[3])));
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tri_aoi21 #(.WIDTH(5)) g04_b_1 (.y(g04_b[1:5]), .a0(t02[1:5]), .a1(g02[3:7]), .b0(g02[1:5]));
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//assign g04_b[6] = (~(g02[6]));
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tri_inv #(.WIDTH(2)) g04_b_6 (.y(g04_b[6:7]), .a(g02[6:7]));
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//assign t04_b[1] = (~(t02[1] & t02[3]));
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tri_nand2 #(.WIDTH(3)) t04_b_1 (.y(t04_b[1:3]), .a(t02[1:3]), .b(t02[3:5]));
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//assign t04_b[4] = (~(g02[4] | (t02[4] & t02[6]))); //final--
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tri_aoi21 #(.WIDTH(2)) t04_b_4 (.y(t04_b[4:5]), .a0(t02[4:5]), .a1(t02[6:7]), .b0(g02[4:5]));
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//assign t04_b[6] = (~(t02[6]));
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tri_inv #(.WIDTH(2)) t04_b_6 (.y(t04_b[6:7]), .a(t02[6:7]));
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//assign g08[1] = (~(g04_b[1] & (t04_b[1] | g04_b[5]))); //final--
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tri_oai21 #(.WIDTH(3)) g08_1 (.y(g08[1:3]), .a0(t04_b[1:3]), .a1(g04_b[5:7]), .b0(g04_b[1:3]));
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//assign g08[4] = (~(g04_b[4]));
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tri_inv #(.WIDTH(4)) g08_4 (.y(g08[4:7]), .a(g04_b[4:7]));
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//assign t08[1] = (~(g04_b[1] & (t04_b[1] | t04_b[5]))); //final--
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tri_oai21 #(.WIDTH(3)) t08_1 (.y(t08[1:3]), .a0(t04_b[1:3]), .a1(t04_b[5:7]), .b0(g04_b[1:3]));
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//assign t08[4] = (~(t04_b[4]));
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tri_inv #(.WIDTH(4)) t08_4 (.y(t08[4:7]), .a(t04_b[4:7]));
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//####################################################################
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//# conditional sums // may need to make NON-xor implementation
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//####################################################################
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//assign g08_b[1] = (~g08[1]);
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tri_inv #(.WIDTH(7)) g08_b_1 (.y(g08_b[1:7]), .a(g08[1:7]));
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//assign t08_b[1] = (~t08[1]);
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tri_inv #(.WIDTH(7)) t08_b_1 (.y(t08_b[1:7]), .a(t08[1:7]));
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//assign sum_0[0] = (~((h01[0] & g08[1]) | (h01_b[0] & g08_b[1]))); //output--
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tri_aoi22 #(.WIDTH(7)) sum_0_0 (.y(sum_0[0:6]), .a0(h01[0:6]), .a1(g08[1:7]), .b0(h01_b[0:6]), .b1(g08_b[1:7]));
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//assign sum_0[7] = (~(h01_b[7])); //output--
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tri_inv sum_0_7 (.y(sum_0[7]), .a(h01_b[7]));
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//assign sum_1[0] = (~((h01[0] & t08[1]) | (h01_b[0] & t08_b[1]))); //output--
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tri_aoi22 #(.WIDTH(7)) sum_1_0 (.y(sum_1[0:6]), .a0(h01[0:6]), .a1(t08[1:7]), .b0(h01_b[0:6]), .b1(t08_b[1:7]));
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//assign sum_1[7] = (~(h01[7])); //output--
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tri_inv sum_1_7 (.y(sum_1[7]), .a(h01[7]));
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endmodule
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