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105 lines
3.8 KiB
Verilog
105 lines
3.8 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// Description: XU SPR - DAC Enable Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module lq_spr_dacen(
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spr_msr_pr,
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spr_msr_ds,
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spr_dbcr0_dac,
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spr_dbcr_dac_us,
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spr_dbcr_dac_er,
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val,
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load,
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store,
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dacr_en,
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dacw_en
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);
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//-------------------------------------------------------------------
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// Generics
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//-------------------------------------------------------------------
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//parameter `THREADS = 4;
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input [0:`THREADS-1] spr_msr_pr;
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input [0:`THREADS-1] spr_msr_ds;
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input [0:2*`THREADS-1] spr_dbcr0_dac;
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input [0:2*`THREADS-1] spr_dbcr_dac_us;
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input [0:2*`THREADS-1] spr_dbcr_dac_er;
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input [0:`THREADS-1] val;
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input load;
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input store;
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output [0:`THREADS-1] dacr_en;
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output [0:`THREADS-1] dacw_en;
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// Signals
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wire [0:1] spr_dbcr0_dac_tid[0:`THREADS-1];
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wire [0:1] spr_dbcr_dac_us_tid[0:`THREADS-1];
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wire [0:1] spr_dbcr_dac_er_tid[0:`THREADS-1];
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wire [0:`THREADS-1] dac_ld_en;
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wire [0:`THREADS-1] dac_st_en;
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wire [0:`THREADS-1] dac_us_en;
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wire [0:`THREADS-1] dac_er_en;
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generate begin : sprTid
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genvar tid;
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for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
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assign spr_dbcr0_dac_tid[tid] = spr_dbcr0_dac[tid*2:tid*2+1];
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assign spr_dbcr_dac_us_tid[tid] = spr_dbcr_dac_us[tid*2:tid*2+1];
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assign spr_dbcr_dac_er_tid[tid] = spr_dbcr_dac_er[tid*2:tid*2+1];
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end
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end
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endgenerate
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generate begin : dacen_gen
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genvar t;
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for (t = 0; t <= `THREADS - 1; t = t + 1) begin : dacen_gen
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assign dac_ld_en[t] = spr_dbcr0_dac_tid[t][0] & load;
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assign dac_st_en[t] = spr_dbcr0_dac_tid[t][1] & store;
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assign dac_us_en[t] = ((~spr_dbcr_dac_us_tid[t][0]) & (~spr_dbcr_dac_us_tid[t][1])) | (spr_dbcr_dac_us_tid[t][0] & (spr_dbcr_dac_us_tid[t][1] ~^ spr_msr_pr[t]));
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assign dac_er_en[t] = ((~spr_dbcr_dac_er_tid[t][0]) & (~spr_dbcr_dac_er_tid[t][1])) | (spr_dbcr_dac_er_tid[t][0] & (spr_dbcr_dac_er_tid[t][1] ~^ spr_msr_ds[t]));
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assign dacr_en[t] = val[t] & dac_ld_en[t] & dac_us_en[t] & dac_er_en[t];
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assign dacw_en[t] = val[t] & dac_st_en[t] & dac_us_en[t] & dac_er_en[t];
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end
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end
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endgenerate
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endmodule
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