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94 lines
3.1 KiB
Verilog
94 lines
3.1 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU SPR - DVC compare component
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module lq_spr_dvccmp(
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en,
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en00,
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cmp,
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dvcm,
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dvcbe,
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dvc_cmpr
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);
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//-------------------------------------------------------------------
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// Generics
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//-------------------------------------------------------------------
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parameter REGSIZE = 64;
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input en;
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input en00;
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input [8-(REGSIZE/8):7] cmp;
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input [0:1] dvcm;
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input [8-(REGSIZE/8):7] dvcbe;
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output dvc_cmpr;
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// Signals
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wire [8-(REGSIZE/8):7] cmp_mask_or;
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wire [8-(REGSIZE/8):7] cmp_mask_and;
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wire cmp_and;
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wire cmp_or;
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wire cmp_andor;
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assign cmp_mask_or = (cmp | (~dvcbe)) & {(REGSIZE/8){|(dvcbe)}};
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assign cmp_mask_and = (cmp & dvcbe);
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assign cmp_and = &(cmp_mask_or);
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assign cmp_or = |(cmp_mask_and);
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generate
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if (REGSIZE == 32) begin : cmp_andor_gen32
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assign cmp_andor = (&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) |
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(&(cmp_mask_or[6:7]) & |(dvcbe[6:7]));
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end
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endgenerate
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generate
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if (REGSIZE == 64) begin : cmp_andor_gen64
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assign cmp_andor = (&(cmp_mask_or[0:1]) & |(dvcbe[0:1])) |
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(&(cmp_mask_or[2:3]) & |(dvcbe[2:3])) |
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(&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) |
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(&(cmp_mask_or[6:7]) & |(dvcbe[6:7]));
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end
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endgenerate
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assign dvc_cmpr = (dvcm[0:1] == 2'b00) ? en00 :
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(dvcm[0:1] == 2'b01) ? (en & cmp_and) :
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(dvcm[0:1] == 2'b10) ? (en & cmp_or) :
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(en & cmp_andor);
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endmodule
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