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104 lines
4.0 KiB
Verilog
104 lines
4.0 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//
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// Description: XU LSU Store Data Mux
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//*****************************************************************************
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module lq_stq_rot(
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rot_sel,
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mask,
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se_b,
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rot_data,
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data_rot
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);
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input [0:3] rot_sel;
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input [0:3] mask;
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input se_b;
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input [0:7] rot_data;
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output [0:7] data_rot;
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wire [0:5] se1;
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wire [0:7] mx1_d0;
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wire [0:7] mx1_d1;
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wire [0:7] mx1_d2;
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wire [0:7] mx1_d3;
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wire [0:7] mx1_s0;
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wire [0:7] mx1_s1;
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wire [0:7] mx1_s2;
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wire [0:7] mx1_s3;
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wire [0:7] mx1_0_b;
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wire [0:7] mx1_1_b;
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wire [0:7] mx1;
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wire [0:7] mask_exp;
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//--------------------------------------------------------------------------------------
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// Muxing <0,2,4,6 bytes>
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//--------------------------------------------------------------------------------------
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assign mx1_s0[0:7] = {8{rot_sel[0]}};
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assign mx1_s1[0:7] = {8{rot_sel[1]}};
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assign mx1_s2[0:7] = {8{rot_sel[2]}};
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assign mx1_s3[0:7] = {8{rot_sel[3]}};
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// Generate a Mask that is dependent on the size of the operation
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assign mask_exp[0] = mask[0]; // 8B
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assign mask_exp[1] = mask[0]; // 8B
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assign mask_exp[2] = mask[0]; // 8B
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assign mask_exp[3] = mask[0]; // 8B
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assign mask_exp[4] = mask[0] | mask[1]; // 8B/4B
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assign mask_exp[5] = mask[0] | mask[1]; // 8B/4B
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assign mask_exp[6] = mask[0] | mask[1] | mask[2]; // 8B/4B/2B
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assign mask_exp[7] = mask[0] | mask[1] | mask[2] | mask[3]; // 8B/4B/2B/1B
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assign se1[0:3] = {4{((~se_b))}};
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assign se1[4:5] = {2{(((~se_b)) & mask[2])}};
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assign mx1_d0 = (rot_data[0:7]) & mask_exp;
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assign mx1_d1 = ({2'b0, rot_data[0:5]}) & mask_exp;
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assign mx1_d2 = ({4'b0, rot_data[0:3]}) & mask_exp;
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assign mx1_d3 = ({6'b0, rot_data[0:1]}) & mask_exp;
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//assign mx1_0_b[0:7] = (~((mx1_s0[0:7] & mx1_d0[0:7]) | (mx1_s1[0:7] & mx1_d1[0:7])));
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tri_aoi22 #(.WIDTH(8)) mx1_0_b_0 (.y(mx1_0_b[0:7]), .a0(mx1_s0[0:7]), .a1(mx1_d0[0:7]), .b0(mx1_s1[0:7]), .b1(mx1_d1[0:7]));
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//assign mx1_1_b[0:7] = (~((mx1_s2[0:7] & mx1_d2[0:7]) | (mx1_s3[0:7] & mx1_d3[0:7])));
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tri_aoi22 #(.WIDTH(8)) mx1_1_b_0 (.y(mx1_1_b[0:7]), .a0(mx1_s2[0:7]), .a1(mx1_d2[0:7]), .b0(mx1_s3[0:7]), .b1(mx1_d3[0:7]));
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//assign mx1[0:7] = (~(mx1_0_b[0:7] & mx1_1_b[0:7]));
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tri_nand2 #(.WIDTH(8)) mx1_0 (.y(mx1[0:7]), .a(mx1_0_b[0:7]), .b(mx1_1_b[0:7]));
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assign data_rot = {(mx1[0:5] | se1[0:5]), mx1[6:7]};
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endmodule
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