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246 lines
9.0 KiB
Verilog
246 lines
9.0 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: Pervasive Core LCB Control Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module pcq_clks_ctrl(
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// Include model build parameters
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`include "tri_a2o.vh"
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inout vdd,
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inout gnd,
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input [0:`NCLK_WIDTH-1] nclk,
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input rtim_sl_thold_6,
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input func_sl_thold_6,
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input func_nsl_thold_6,
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input ary_nsl_thold_6,
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input sg_6,
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input fce_6,
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input gsd_test_enable_dc,
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input gsd_test_acmode_dc,
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input ccflush_dc,
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input ccenable_dc,
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input lbist_en_dc,
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input lbist_ip_dc,
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input rg_ck_fast_xstop,
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input ct_ck_pm_ccflush_disable,
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input ct_ck_pm_raise_tholds,
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input [0:8] scan_type_dc,
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// --Thold + control outputs to the units
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output ccflush_out_dc,
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output gptr_sl_thold_5,
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output time_sl_thold_5,
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output repr_sl_thold_5,
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output cfg_sl_thold_5,
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output cfg_slp_sl_thold_5,
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output abst_sl_thold_5,
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output abst_slp_sl_thold_5,
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output regf_sl_thold_5,
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output regf_slp_sl_thold_5,
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output func_sl_thold_5,
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output func_slp_sl_thold_5,
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output func_nsl_thold_5,
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output func_slp_nsl_thold_5,
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output ary_nsl_thold_5,
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output ary_slp_nsl_thold_5,
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output rtim_sl_thold_5,
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output sg_5,
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output fce_5
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);
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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// Scan ring select decodes for scan_type_dc vector
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parameter SCANTYPE_SIZE = 9; // Use bits 0:8 of scan_type vector
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parameter SCANTYPE_FUNC = 0;
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parameter SCANTYPE_MODE = 1;
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parameter SCANTYPE_CCFG = 2;
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parameter SCANTYPE_GPTR = 2;
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parameter SCANTYPE_REGF = 3;
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parameter SCANTYPE_FUSE = 3;
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parameter SCANTYPE_LBST = 4;
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parameter SCANTYPE_ABST = 5;
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parameter SCANTYPE_REPR = 6;
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parameter SCANTYPE_TIME = 7;
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parameter SCANTYPE_BNDY = 8;
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parameter SCANTYPE_FARY = 9;
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wire fast_xstop_gated_staged;
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wire fce_in;
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wire sg_in;
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wire ary_nsl_thold;
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wire func_nsl_thold;
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wire rtim_sl_thold;
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wire func_sl_thold;
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wire gptr_sl_thold_in;
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wire time_sl_thold_in;
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wire repr_sl_thold_in;
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wire rtim_sl_thold_in;
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wire cfg_run_sl_thold_in;
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wire cfg_slp_sl_thold_in;
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wire abst_run_sl_thold_in;
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wire abst_slp_sl_thold_in;
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wire regf_run_sl_thold_in;
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wire regf_slp_sl_thold_in;
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wire func_run_sl_thold_in;
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wire func_slp_sl_thold_in;
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wire func_run_nsl_thold_in;
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wire func_slp_nsl_thold_in;
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wire ary_run_nsl_thold_in;
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wire ary_slp_nsl_thold_in;
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wire pm_ccflush_disable_dc;
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wire ccflush_out_dc_int;
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wire testdc;
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wire thold_overide_ctrl;
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wire [0:SCANTYPE_SIZE-1] scan_type_b;
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(* analysis_not_referenced="true" *)
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wire unused_signals;
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assign unused_signals = (scan_type_b[2] | scan_type_b[4] | (|scan_type_b[6:8]) | lbist_ip_dc);
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//!! Bugspray Include: pcq_clks_ctrl;
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//=====================================================================
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// Clock Control Logic
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//=====================================================================
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// detect test dc mode
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assign testdc = gsd_test_enable_dc & (~gsd_test_acmode_dc);
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// enable sg/fce before latching
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assign sg_in = sg_6 & ccenable_dc;
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assign fce_in = fce_6 & ccenable_dc;
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// scan chain type
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assign scan_type_b = ({SCANTYPE_SIZE {sg_in}} & (~scan_type_dc));
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// setup for xx_thold_6 inputs
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assign thold_overide_ctrl = fast_xstop_gated_staged & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc);
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assign rtim_sl_thold = rtim_sl_thold_6;
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assign func_sl_thold = func_sl_thold_6 | thold_overide_ctrl;
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assign func_nsl_thold = func_nsl_thold_6 | thold_overide_ctrl;
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assign ary_nsl_thold = ary_nsl_thold_6 | thold_overide_ctrl;
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// setup for plat flush control signals
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// Active when power_management enabled (PM_Sleep_enable or PM_RVW_enable active)
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// If plats were in flush mode, forces plats to be clocked again for power-savings.
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assign pm_ccflush_disable_dc = ct_ck_pm_ccflush_disable;
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assign ccflush_out_dc_int = ccflush_dc & ((~pm_ccflush_disable_dc) | lbist_en_dc | testdc);
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assign ccflush_out_dc = ccflush_out_dc_int;
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// OR and MUX of thold signals
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// scan only: stop if not scanning, not part of LBIST, hence no sg_in here
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assign gptr_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_GPTR]) | (~ccenable_dc);
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// scan only: stop if not scanning, not part of LBIST, hence no sg_in here
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assign time_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_TIME]) | (~ccenable_dc);
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// scan only: stop if not scanning, not part of LBIST, hence no sg_in here
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assign repr_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_REPR]) | (~ccenable_dc);
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assign cfg_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_MODE] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
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assign cfg_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_MODE];
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assign abst_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_ABST] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
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assign abst_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_ABST];
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assign regf_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_REGF] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
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assign regf_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_REGF];
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assign func_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_FUNC] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
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assign func_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_FUNC];
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assign func_run_nsl_thold_in = func_nsl_thold | (ct_ck_pm_raise_tholds & (~fce_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
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assign func_slp_nsl_thold_in = func_nsl_thold;
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assign ary_run_nsl_thold_in = ary_nsl_thold | (ct_ck_pm_raise_tholds & (~fce_in) & (~lbist_en_dc) & (~gsd_test_enable_dc));
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assign ary_slp_nsl_thold_in = ary_nsl_thold;
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assign rtim_sl_thold_in = rtim_sl_thold;
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// PLAT staging/redrive
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tri_plat #(.WIDTH(1)) fast_stop_staging(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc_int),
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.din(rg_ck_fast_xstop),
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.q(fast_xstop_gated_staged)
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);
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tri_plat #(.WIDTH(2)) sg_fce_plat(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc_int),
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.din({sg_in, fce_in}),
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.q ({sg_5, fce_5 })
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);
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tri_plat #(.WIDTH(16)) thold_plat(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc_int),
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.din({gptr_sl_thold_in, time_sl_thold_in, repr_sl_thold_in, cfg_run_sl_thold_in,
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cfg_slp_sl_thold_in, abst_run_sl_thold_in, abst_slp_sl_thold_in, regf_run_sl_thold_in,
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regf_slp_sl_thold_in, func_run_sl_thold_in, func_slp_sl_thold_in, func_run_nsl_thold_in,
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func_slp_nsl_thold_in, ary_run_nsl_thold_in, ary_slp_nsl_thold_in, rtim_sl_thold_in}),
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.q ({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5, cfg_sl_thold_5,
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cfg_slp_sl_thold_5, abst_sl_thold_5, abst_slp_sl_thold_5, regf_sl_thold_5,
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regf_slp_sl_thold_5, func_sl_thold_5, func_slp_sl_thold_5, func_nsl_thold_5,
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func_slp_nsl_thold_5, ary_nsl_thold_5, ary_slp_nsl_thold_5, rtim_sl_thold_5})
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);
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endmodule
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