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432 lines
15 KiB
Verilog
432 lines
15 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: Pervasive Core LCB Staging
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module pcq_clks_stg(
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// Include model build parameters
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`include "tri_a2o.vh"
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inout vdd,
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inout gnd,
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input [0:`NCLK_WIDTH-1] nclk,
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input ccflush_out_dc,
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input gptr_sl_thold_5,
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input time_sl_thold_5,
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input repr_sl_thold_5,
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input cfg_sl_thold_5,
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input cfg_slp_sl_thold_5,
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input abst_sl_thold_5,
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input abst_slp_sl_thold_5,
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input regf_sl_thold_5,
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input regf_slp_sl_thold_5,
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input func_sl_thold_5,
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input func_slp_sl_thold_5,
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input func_nsl_thold_5,
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input func_slp_nsl_thold_5,
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input ary_nsl_thold_5,
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input ary_slp_nsl_thold_5,
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input rtim_sl_thold_5,
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input sg_5,
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input fce_5,
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// Thold + control outputs to the units
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output pc_pc_ccflush_out_dc,
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output pc_pc_gptr_sl_thold_4,
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output pc_pc_time_sl_thold_4,
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output pc_pc_repr_sl_thold_4,
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output pc_pc_abst_sl_thold_4,
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output pc_pc_abst_slp_sl_thold_4,
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output pc_pc_regf_sl_thold_4,
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output pc_pc_regf_slp_sl_thold_4,
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output pc_pc_func_sl_thold_4,
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output pc_pc_func_slp_sl_thold_4,
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output pc_pc_cfg_sl_thold_4,
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output pc_pc_cfg_slp_sl_thold_4,
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output pc_pc_func_nsl_thold_4,
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output pc_pc_func_slp_nsl_thold_4,
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output pc_pc_ary_nsl_thold_4,
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output pc_pc_ary_slp_nsl_thold_4,
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output pc_pc_rtim_sl_thold_4,
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output pc_pc_sg_4,
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output pc_pc_fce_4,
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// Thold + control signals used by fu
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output pc_fu_ccflush_dc,
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output pc_fu_gptr_sl_thold_3,
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output pc_fu_time_sl_thold_3,
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output pc_fu_repr_sl_thold_3,
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output pc_fu_abst_sl_thold_3,
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output pc_fu_abst_slp_sl_thold_3,
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output [0:1] pc_fu_func_sl_thold_3,
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output [0:1] pc_fu_func_slp_sl_thold_3,
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output pc_fu_cfg_sl_thold_3,
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output pc_fu_cfg_slp_sl_thold_3,
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output pc_fu_func_nsl_thold_3,
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output pc_fu_func_slp_nsl_thold_3,
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output pc_fu_ary_nsl_thold_3,
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output pc_fu_ary_slp_nsl_thold_3,
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output [0:1] pc_fu_sg_3,
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output pc_fu_fce_3,
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// Thold + control signals used in pcq
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output pc_pc_ccflush_dc,
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output pc_pc_gptr_sl_thold_0,
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output pc_pc_func_sl_thold_0,
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output pc_pc_func_slp_sl_thold_0,
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output pc_pc_cfg_sl_thold_0,
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output pc_pc_cfg_slp_sl_thold_0,
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output pc_pc_sg_0
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);
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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wire pc_pc_gptr_sl_thold_4_int;
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wire pc_pc_time_sl_thold_4_int;
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wire pc_pc_repr_sl_thold_4_int;
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wire pc_pc_abst_sl_thold_4_int;
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wire pc_pc_abst_slp_sl_thold_4_int;
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wire pc_pc_regf_sl_thold_4_int;
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wire pc_pc_regf_slp_sl_thold_4_int;
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wire pc_pc_func_sl_thold_4_int;
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wire pc_pc_func_slp_sl_thold_4_int;
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wire pc_pc_cfg_sl_thold_4_int;
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wire pc_pc_cfg_slp_sl_thold_4_int;
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wire pc_pc_func_nsl_thold_4_int;
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wire pc_pc_func_slp_nsl_thold_4_int;
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wire pc_pc_ary_nsl_thold_4_int;
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wire pc_pc_ary_slp_nsl_thold_4_int;
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wire pc_pc_rtim_sl_thold_4_int;
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wire pc_pc_sg_4_int;
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wire pc_pc_fce_4_int;
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wire pc_pc_gptr_sl_thold_3;
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wire pc_pc_abst_sl_thold_3;
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wire pc_pc_func_sl_thold_3;
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wire pc_pc_func_slp_sl_thold_3;
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wire pc_pc_cfg_slp_sl_thold_3;
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wire pc_pc_cfg_sl_thold_3;
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wire pc_pc_sg_3;
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wire pc_pc_gptr_sl_thold_2;
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wire pc_pc_abst_sl_thold_2;
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wire pc_pc_func_sl_thold_2;
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wire pc_pc_func_slp_sl_thold_2;
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wire pc_pc_cfg_slp_sl_thold_2;
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wire pc_pc_cfg_sl_thold_2;
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wire pc_pc_sg_2;
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wire pc_pc_gptr_sl_thold_1;
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wire pc_pc_abst_sl_thold_1;
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wire pc_pc_func_sl_thold_1;
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wire pc_pc_func_slp_sl_thold_1;
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wire pc_pc_cfg_slp_sl_thold_1;
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wire pc_pc_cfg_sl_thold_1;
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wire pc_pc_sg_1;
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//=====================================================================
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// LCB control signals staged/redriven to other units
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//=====================================================================
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assign pc_pc_ccflush_out_dc = ccflush_out_dc;
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assign pc_pc_ccflush_dc = ccflush_out_dc;
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assign pc_fu_ccflush_dc = ccflush_out_dc;
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// Start of thold/SG/FCE staging (level 5 to level 3)
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tri_plat #(.WIDTH(18)) lvl5to4_plat(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5,
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rtim_sl_thold_5, abst_sl_thold_5, abst_slp_sl_thold_5,
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regf_sl_thold_5, regf_slp_sl_thold_5, func_sl_thold_5,
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func_slp_sl_thold_5, cfg_sl_thold_5, cfg_slp_sl_thold_5,
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func_nsl_thold_5, func_slp_nsl_thold_5, ary_nsl_thold_5,
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ary_slp_nsl_thold_5, sg_5, fce_5}),
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.q( {pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int,
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pc_pc_rtim_sl_thold_4_int, pc_pc_abst_sl_thold_4_int, pc_pc_abst_slp_sl_thold_4_int,
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pc_pc_regf_sl_thold_4_int, pc_pc_regf_slp_sl_thold_4_int, pc_pc_func_sl_thold_4_int,
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pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int, pc_pc_cfg_slp_sl_thold_4_int,
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pc_pc_func_nsl_thold_4_int, pc_pc_func_slp_nsl_thold_4_int, pc_pc_ary_nsl_thold_4_int,
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pc_pc_ary_slp_nsl_thold_4_int, pc_pc_sg_4_int, pc_pc_fce_4_int})
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);
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// Level 4 staging goes to the pervasive repower logic
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assign pc_pc_gptr_sl_thold_4 = pc_pc_gptr_sl_thold_4_int;
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assign pc_pc_time_sl_thold_4 = pc_pc_time_sl_thold_4_int;
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assign pc_pc_repr_sl_thold_4 = pc_pc_repr_sl_thold_4_int;
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assign pc_pc_abst_sl_thold_4 = pc_pc_abst_sl_thold_4_int;
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assign pc_pc_abst_slp_sl_thold_4 = pc_pc_abst_slp_sl_thold_4_int;
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assign pc_pc_regf_sl_thold_4 = pc_pc_regf_sl_thold_4_int;
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assign pc_pc_regf_slp_sl_thold_4 = pc_pc_regf_slp_sl_thold_4_int;
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assign pc_pc_func_sl_thold_4 = pc_pc_func_sl_thold_4_int;
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assign pc_pc_func_slp_sl_thold_4 = pc_pc_func_slp_sl_thold_4_int;
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assign pc_pc_cfg_sl_thold_4 = pc_pc_cfg_sl_thold_4_int;
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assign pc_pc_cfg_slp_sl_thold_4 = pc_pc_cfg_slp_sl_thold_4_int;
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assign pc_pc_func_nsl_thold_4 = pc_pc_func_nsl_thold_4_int;
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assign pc_pc_func_slp_nsl_thold_4 = pc_pc_func_slp_nsl_thold_4_int;
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assign pc_pc_ary_nsl_thold_4 = pc_pc_ary_nsl_thold_4_int;
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assign pc_pc_ary_slp_nsl_thold_4 = pc_pc_ary_slp_nsl_thold_4_int;
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assign pc_pc_rtim_sl_thold_4 = pc_pc_rtim_sl_thold_4_int;
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assign pc_pc_sg_4 = pc_pc_sg_4_int;
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assign pc_pc_fce_4 = pc_pc_fce_4_int;
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// FU clock control staging: level 4 to 3
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tri_plat #(.WIDTH(18)) fu_clkstg_4to3(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din({pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int,
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pc_pc_abst_sl_thold_4_int, pc_pc_abst_slp_sl_thold_4_int, pc_pc_func_sl_thold_4_int,
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pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int,
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pc_pc_cfg_sl_thold_4_int, pc_pc_cfg_slp_sl_thold_4_int, pc_pc_func_nsl_thold_4_int,
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pc_pc_func_slp_nsl_thold_4_int, pc_pc_ary_nsl_thold_4_int, pc_pc_ary_slp_nsl_thold_4_int,
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pc_pc_sg_4_int, pc_pc_sg_4_int, pc_pc_fce_4_int }),
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.q( {pc_fu_gptr_sl_thold_3, pc_fu_time_sl_thold_3, pc_fu_repr_sl_thold_3,
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pc_fu_abst_sl_thold_3, pc_fu_abst_slp_sl_thold_3, pc_fu_func_sl_thold_3[0],
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pc_fu_func_sl_thold_3[1], pc_fu_func_slp_sl_thold_3[0], pc_fu_func_slp_sl_thold_3[1],
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pc_fu_cfg_sl_thold_3, pc_fu_cfg_slp_sl_thold_3, pc_fu_func_nsl_thold_3,
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pc_fu_func_slp_nsl_thold_3, pc_fu_ary_nsl_thold_3, pc_fu_ary_slp_nsl_thold_3,
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pc_fu_sg_3[0], pc_fu_sg_3[1], pc_fu_fce_3 })
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);
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// PC clock control staging: level 4 to 3
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tri_plat #(.WIDTH(6)) pc_lvl4to3(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din({pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int,
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pc_pc_cfg_slp_sl_thold_4_int, pc_pc_gptr_sl_thold_4_int, pc_pc_sg_4_int}),
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.q( {pc_pc_func_sl_thold_3, pc_pc_func_slp_sl_thold_3, pc_pc_cfg_sl_thold_3,
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pc_pc_cfg_slp_sl_thold_3, pc_pc_gptr_sl_thold_3, pc_pc_sg_3})
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);
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// End of thold/SG/FCE staging (level 5 to level 3)
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//=====================================================================
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// thold/SG staging (level 3 to level 0) for PC units
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//=====================================================================
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//----------------------------------------------------
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// FUNC (RUN)
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//----------------------------------------------------
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tri_plat #(.WIDTH(1)) func_3_2(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_func_sl_thold_3),
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.q(pc_pc_func_sl_thold_2)
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);
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tri_plat #(.WIDTH(1)) func_2_1(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_func_sl_thold_2),
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.q(pc_pc_func_sl_thold_1)
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);
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tri_plat #(.WIDTH(1)) func_1_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_func_sl_thold_1),
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.q(pc_pc_func_sl_thold_0)
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);
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//----------------------------------------------------
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// FUNC (SLEEP)
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//----------------------------------------------------
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tri_plat #(.WIDTH(1)) func_slp_3_2(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_func_slp_sl_thold_3),
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.q(pc_pc_func_slp_sl_thold_2)
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);
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tri_plat #(.WIDTH(1)) func_slp_2_1(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_func_slp_sl_thold_2),
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.q(pc_pc_func_slp_sl_thold_1)
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);
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tri_plat #(.WIDTH(1)) func_slp_1_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_func_slp_sl_thold_1),
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.q(pc_pc_func_slp_sl_thold_0)
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);
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//----------------------------------------------------
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// CFG (RUN)
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//----------------------------------------------------
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tri_plat #(.WIDTH(1)) cfg_3_2(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_cfg_sl_thold_3),
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.q(pc_pc_cfg_sl_thold_2)
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);
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tri_plat #(.WIDTH(1)) cfg_2_1(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_cfg_sl_thold_2),
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.q(pc_pc_cfg_sl_thold_1)
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);
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tri_plat #(.WIDTH(1)) cfg_1_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_cfg_sl_thold_1),
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.q(pc_pc_cfg_sl_thold_0)
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);
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//----------------------------------------------------
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// CFG (SLEEP)
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//----------------------------------------------------
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tri_plat #(.WIDTH(1)) cfg_slp_3_2(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_cfg_slp_sl_thold_3),
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.q(pc_pc_cfg_slp_sl_thold_2)
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);
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tri_plat #(.WIDTH(1)) cfg_slp_2_1(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_cfg_slp_sl_thold_2),
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.q(pc_pc_cfg_slp_sl_thold_1)
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);
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tri_plat #(.WIDTH(1)) cfg_slp_1_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_cfg_slp_sl_thold_1),
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.q(pc_pc_cfg_slp_sl_thold_0)
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);
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//----------------------------------------------------
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// GPTR
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//----------------------------------------------------
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tri_plat #(.WIDTH(1)) gptr_3_2(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_out_dc),
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.din(pc_pc_gptr_sl_thold_3),
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.q(pc_pc_gptr_sl_thold_2)
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);
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tri_plat #(.WIDTH(1)) gptr_2_1(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
|
|
.flush(ccflush_out_dc),
|
|
.din(pc_pc_gptr_sl_thold_2),
|
|
.q(pc_pc_gptr_sl_thold_1)
|
|
);
|
|
|
|
tri_plat #(.WIDTH(1)) gptr_1_0(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(ccflush_out_dc),
|
|
.din(pc_pc_gptr_sl_thold_1),
|
|
.q(pc_pc_gptr_sl_thold_0)
|
|
);
|
|
|
|
//----------------------------------------------------
|
|
// SG
|
|
//----------------------------------------------------
|
|
tri_plat #(.WIDTH(1)) sg_3_2(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(ccflush_out_dc),
|
|
.din(pc_pc_sg_3),
|
|
.q(pc_pc_sg_2)
|
|
);
|
|
|
|
tri_plat #(.WIDTH(1)) sg_2_1(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(ccflush_out_dc),
|
|
.din(pc_pc_sg_2),
|
|
.q(pc_pc_sg_1)
|
|
);
|
|
|
|
tri_plat #(.WIDTH(1)) sg_1_0(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(ccflush_out_dc),
|
|
.din(pc_pc_sg_1),
|
|
.q(pc_pc_sg_0)
|
|
);
|
|
|
|
|
|
endmodule
|