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281 lines
12 KiB
Verilog
281 lines
12 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: Mapped Itag Compare
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//
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//*****************************************************************************
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module rv_cmpitag(
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vld,
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itag,
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vld_ary,
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itag_ary,
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abort,
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hit_clear,
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hit_abort
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);
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`include "tri_a2o.vh"
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parameter q_itag_busses_g = 7;
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input [0:`THREADS-1] vld;
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input [0:`ITAG_SIZE_ENC-1] itag;
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input [0:(q_itag_busses_g*`THREADS)-1] vld_ary;
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input [0:(q_itag_busses_g*`ITAG_SIZE_ENC)-1] itag_ary;
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input [0:q_itag_busses_g-1] abort;
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output hit_clear;
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output hit_abort;
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wire [0:7] valid;
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wire [0:7] itag_xor[0:7];
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wire [0:3] itag_andl10_b;
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wire [0:3] itag_andl11_b;
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wire [0:3] itag_andl12_b;
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wire [0:3] itag_andl13_b;
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wire [0:3] itag_andl14_b;
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wire [0:3] itag_andl15_b;
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wire [0:3] itag_andl16_b;
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wire [0:3] itag_andl17_b;
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wire [0:1] itag_andl20;
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wire [0:1] itag_andl21;
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wire [0:1] itag_andl22;
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wire [0:1] itag_andl23;
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wire [0:1] itag_andl24;
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wire [0:1] itag_andl25;
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wire [0:1] itag_andl26;
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wire [0:1] itag_andl27;
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wire [0:7] itagc_andl3_b;
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wire [0:3] itagc_orl4;
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wire [0:1] itagc_orl5_b;
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wire itagc_orl6;
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wire [0:7] itaga_andl3_b;
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wire [0:3] itaga_orl4;
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wire [0:1] itaga_orl5_b;
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wire itaga_orl6;
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wire [0:7] itag_abort;
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wire [0:7] itag_abort_b;
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(* analysis_not_referenced="true" *)
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wire unused;
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//-------------------------------------------------------------------------------------------------------
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// Total Logic: XOR + 6 levels
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//-------------------------------------------------------------------------------------------------------
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generate
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begin : xhdl0
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genvar n;
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for (n = 0; n <= 5; n = n + 1)
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begin : q_valid_gen
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assign valid[n] = |(vld_ary[n*`THREADS:n*`THREADS+`THREADS-1] & vld);
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assign itag_xor[n] = {~(itag ^ itag_ary[n*`ITAG_SIZE_ENC:n*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[n]};
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end
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end
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endgenerate
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//-------------------------------------------------------------------------------------------------------
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// XOR ITAG Compares
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//-------------------------------------------------------------------------------------------------------
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assign itag_abort[0:5] = abort[0:5];
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generate
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if (q_itag_busses_g == 6)
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begin : l1xor_gen6
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assign itag_xor[6] = {8{1'b0}};
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assign itag_xor[7] = {8{1'b0}};
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assign valid[6] = 1'b0;
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assign valid[7] = 1'b0;
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assign itag_abort[6] = 1'b0;
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assign itag_abort[7] = 1'b0;
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end
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endgenerate
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generate
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if (q_itag_busses_g == 7)
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begin : l1xor_gen7
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assign itag_xor[6] = {~(itag ^ itag_ary[6*`ITAG_SIZE_ENC:6*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[6]};
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assign itag_xor[7] = {8{1'b0}};
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assign valid[6] = |(vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] & vld);
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assign valid[7] = 1'b0;
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assign itag_abort[6] = abort[6];
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assign itag_abort[7] = 1'b0;
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assign unused = valid[7] ;
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end
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endgenerate
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generate
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if (q_itag_busses_g == 8)
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begin : l1xor_gen8
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assign itag_xor[6] = {~(itag ^ itag_ary[6*`ITAG_SIZE_ENC:6*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[6]};
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assign itag_xor[7] = {~(itag ^ itag_ary[7*`ITAG_SIZE_ENC:7*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[7]};
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assign valid[6] = |(vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] & vld);
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assign valid[7] = |(vld_ary[7*`THREADS:7*`THREADS+`THREADS-1] & vld);
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assign itag_abort[6] = abort[6];
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assign itag_abort[7] = abort[7];
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end
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endgenerate
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assign itag_abort_b = ~itag_abort;
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//-------------------------------------------------------------------------------------------------------
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// AND Tree. 8 groups of 8, 3 levels each
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//-------------------------------------------------------------------------------------------------------
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// Level 1
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assign itag_andl10_b[0] = ~(itag_xor[0][0] & itag_xor[0][1]);
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assign itag_andl10_b[1] = ~(itag_xor[0][2] & itag_xor[0][3]);
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assign itag_andl10_b[2] = ~(itag_xor[0][4] & itag_xor[0][5]);
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assign itag_andl10_b[3] = ~(itag_xor[0][6] & itag_xor[0][7]);
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assign itag_andl11_b[0] = ~(itag_xor[1][0] & itag_xor[1][1]);
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assign itag_andl11_b[1] = ~(itag_xor[1][2] & itag_xor[1][3]);
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assign itag_andl11_b[2] = ~(itag_xor[1][4] & itag_xor[1][5]);
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assign itag_andl11_b[3] = ~(itag_xor[1][6] & itag_xor[1][7]);
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assign itag_andl12_b[0] = ~(itag_xor[2][0] & itag_xor[2][1]);
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assign itag_andl12_b[1] = ~(itag_xor[2][2] & itag_xor[2][3]);
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assign itag_andl12_b[2] = ~(itag_xor[2][4] & itag_xor[2][5]);
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assign itag_andl12_b[3] = ~(itag_xor[2][6] & itag_xor[2][7]);
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assign itag_andl13_b[0] = ~(itag_xor[3][0] & itag_xor[3][1]);
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assign itag_andl13_b[1] = ~(itag_xor[3][2] & itag_xor[3][3]);
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assign itag_andl13_b[2] = ~(itag_xor[3][4] & itag_xor[3][5]);
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assign itag_andl13_b[3] = ~(itag_xor[3][6] & itag_xor[3][7]);
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assign itag_andl14_b[0] = ~(itag_xor[4][0] & itag_xor[4][1]);
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assign itag_andl14_b[1] = ~(itag_xor[4][2] & itag_xor[4][3]);
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assign itag_andl14_b[2] = ~(itag_xor[4][4] & itag_xor[4][5]);
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assign itag_andl14_b[3] = ~(itag_xor[4][6] & itag_xor[4][7]);
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assign itag_andl15_b[0] = ~(itag_xor[5][0] & itag_xor[5][1]);
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assign itag_andl15_b[1] = ~(itag_xor[5][2] & itag_xor[5][3]);
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assign itag_andl15_b[2] = ~(itag_xor[5][4] & itag_xor[5][5]);
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assign itag_andl15_b[3] = ~(itag_xor[5][6] & itag_xor[5][7]);
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assign itag_andl16_b[0] = ~(itag_xor[6][0] & itag_xor[6][1]);
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assign itag_andl16_b[1] = ~(itag_xor[6][2] & itag_xor[6][3]);
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assign itag_andl16_b[2] = ~(itag_xor[6][4] & itag_xor[6][5]);
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assign itag_andl16_b[3] = ~(itag_xor[6][6] & itag_xor[6][7]);
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assign itag_andl17_b[0] = ~(itag_xor[7][0] & itag_xor[7][1]);
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assign itag_andl17_b[1] = ~(itag_xor[7][2] & itag_xor[7][3]);
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assign itag_andl17_b[2] = ~(itag_xor[7][4] & itag_xor[7][5]);
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assign itag_andl17_b[3] = ~(itag_xor[7][6] & itag_xor[7][7]);
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// Level 2
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assign itag_andl20[0] = ~(itag_andl10_b[0] | itag_andl10_b[1]);
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assign itag_andl20[1] = ~(itag_andl10_b[2] | itag_andl10_b[3]);
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assign itag_andl21[0] = ~(itag_andl11_b[0] | itag_andl11_b[1]);
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assign itag_andl21[1] = ~(itag_andl11_b[2] | itag_andl11_b[3]);
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assign itag_andl22[0] = ~(itag_andl12_b[0] | itag_andl12_b[1]);
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assign itag_andl22[1] = ~(itag_andl12_b[2] | itag_andl12_b[3]);
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assign itag_andl23[0] = ~(itag_andl13_b[0] | itag_andl13_b[1]);
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assign itag_andl23[1] = ~(itag_andl13_b[2] | itag_andl13_b[3]);
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assign itag_andl24[0] = ~(itag_andl14_b[0] | itag_andl14_b[1]);
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assign itag_andl24[1] = ~(itag_andl14_b[2] | itag_andl14_b[3]);
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assign itag_andl25[0] = ~(itag_andl15_b[0] | itag_andl15_b[1]);
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assign itag_andl25[1] = ~(itag_andl15_b[2] | itag_andl15_b[3]);
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assign itag_andl26[0] = ~(itag_andl16_b[0] | itag_andl16_b[1]);
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assign itag_andl26[1] = ~(itag_andl16_b[2] | itag_andl16_b[3]);
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assign itag_andl27[0] = ~(itag_andl17_b[0] | itag_andl17_b[1]);
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assign itag_andl27[1] = ~(itag_andl17_b[2] | itag_andl17_b[3]);
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// Level 3 - sneak in the abort here
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assign itagc_andl3_b[0] = ~(itag_andl20[0] & itag_andl20[1] & itag_abort_b[0]);
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assign itagc_andl3_b[1] = ~(itag_andl21[0] & itag_andl21[1] & itag_abort_b[1]);
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assign itagc_andl3_b[2] = ~(itag_andl22[0] & itag_andl22[1] & itag_abort_b[2]);
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assign itagc_andl3_b[3] = ~(itag_andl23[0] & itag_andl23[1] & itag_abort_b[3]);
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assign itagc_andl3_b[4] = ~(itag_andl24[0] & itag_andl24[1] & itag_abort_b[4]);
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assign itagc_andl3_b[5] = ~(itag_andl25[0] & itag_andl25[1] & itag_abort_b[5]);
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assign itagc_andl3_b[6] = ~(itag_andl26[0] & itag_andl26[1] & itag_abort_b[6]);
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assign itagc_andl3_b[7] = ~(itag_andl27[0] & itag_andl27[1] & itag_abort_b[7]);
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// Level 3 - sneak in the abort here
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assign itaga_andl3_b[0] = ~(itag_andl20[0] & itag_andl20[1] & itag_abort[0]);
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assign itaga_andl3_b[1] = ~(itag_andl21[0] & itag_andl21[1] & itag_abort[1]);
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assign itaga_andl3_b[2] = ~(itag_andl22[0] & itag_andl22[1] & itag_abort[2]);
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assign itaga_andl3_b[3] = ~(itag_andl23[0] & itag_andl23[1] & itag_abort[3]);
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assign itaga_andl3_b[4] = ~(itag_andl24[0] & itag_andl24[1] & itag_abort[4]);
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assign itaga_andl3_b[5] = ~(itag_andl25[0] & itag_andl25[1] & itag_abort[5]);
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assign itaga_andl3_b[6] = ~(itag_andl26[0] & itag_andl26[1] & itag_abort[6]);
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assign itaga_andl3_b[7] = ~(itag_andl27[0] & itag_andl27[1] & itag_abort[7]);
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//-------------------------------------------------------------------------------------------------------
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// CLEAR OR Tree. 8 groups. Coming in inverted. 3 more levels
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//-------------------------------------------------------------------------------------------------------
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// Level 4
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assign itagc_orl4[0] = ~(itagc_andl3_b[0] & itagc_andl3_b[1]);
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assign itagc_orl4[1] = ~(itagc_andl3_b[2] & itagc_andl3_b[3]);
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assign itagc_orl4[2] = ~(itagc_andl3_b[4] & itagc_andl3_b[5]);
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assign itagc_orl4[3] = ~(itagc_andl3_b[6] & itagc_andl3_b[7]);
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// Level 5
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assign itagc_orl5_b[0] = ~(itagc_orl4[0] | itagc_orl4[1]);
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assign itagc_orl5_b[1] = ~(itagc_orl4[2] | itagc_orl4[3]);
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// Level 6
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assign itagc_orl6 = ~(itagc_orl5_b[0] & itagc_orl5_b[1]);
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assign hit_clear = itagc_orl6;
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//-------------------------------------------------------------------------------------------------------
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// ABORT OR Tree. 8 groups. Coming in inverted. 3 more levels
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//-------------------------------------------------------------------------------------------------------
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// Level 4
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assign itaga_orl4[0] = ~(itaga_andl3_b[0] & itaga_andl3_b[1]);
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assign itaga_orl4[1] = ~(itaga_andl3_b[2] & itaga_andl3_b[3]);
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assign itaga_orl4[2] = ~(itaga_andl3_b[4] & itaga_andl3_b[5]);
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assign itaga_orl4[3] = ~(itaga_andl3_b[6] & itaga_andl3_b[7]);
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// Level 5
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assign itaga_orl5_b[0] = ~(itaga_orl4[0] | itaga_orl4[1]);
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assign itaga_orl5_b[1] = ~(itaga_orl4[2] | itaga_orl4[3]);
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// Level 6
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assign itaga_orl6 = ~(itaga_orl5_b[0] & itaga_orl5_b[1]);
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assign hit_abort = itaga_orl6;
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endmodule // rv_cmpitag
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