You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
55 lines
2.8 KiB
Verilog
55 lines
2.8 KiB
Verilog
// © IBM Corp. 2020
|
|
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
|
// the terms below; you may not use the files in this repository except in
|
|
// compliance with the License as modified.
|
|
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Modified Terms:
|
|
//
|
|
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
|
// License, the "Work" hereby includes implementations of the work of authorship
|
|
// in physical form.
|
|
//
|
|
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
|
// necessary for implementation of the Work that are available from OpenPOWER
|
|
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
|
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
|
// of the EULA.
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, the reference design
|
|
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
|
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
|
// for the specific language governing permissions and limitations under the License.
|
|
//
|
|
// Additional rights, including the ability to physically implement a softcore that
|
|
// is compliant with the required sections of the Power ISA Specification, are
|
|
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
|
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
|
|
|
`timescale 1 ns / 1 ns
|
|
|
|
//*****************************************************************************
|
|
// Description: XU DPD to BCD Conversion
|
|
//
|
|
//*****************************************************************************
|
|
|
|
module xu0_bcd_dtbcd(
|
|
input [0:9] a,
|
|
output [0:11] y
|
|
);
|
|
|
|
assign y[0] = ((~a[3]) & a[6] & a[7]) | (a[4] & a[6] & a[7] & a[3]) | (a[6] & a[7] & (~a[8]));
|
|
assign y[1] = (a[0] & a[3] & a[8] & (~a[4])) | (a[0] & (~a[7])) | (a[0] & (~a[6]));
|
|
assign y[2] = (a[1] & a[3] & a[8] & (~a[4])) | (a[1] & (~a[7])) | (a[1] & (~a[6]));
|
|
assign y[3] = a[2];
|
|
assign y[4] = (a[6] & (~a[7]) & a[8]) | (a[3] & a[6] & a[7] & a[8]) | ((~a[4]) & a[6] & a[8] & a[7]);
|
|
assign y[5] = (a[0] & a[4] & a[6] & a[7] & a[8] & (~a[3])) | (a[3] & (~a[8]) & a[6]) | (a[3] & (~a[6]));
|
|
assign y[6] = (a[1] & a[4] & a[7] & a[6] & a[8] & (~a[3])) | (a[4] & (~a[8]) & a[6]) | (a[4] & (~a[6]));
|
|
assign y[7] = a[5];
|
|
assign y[8] = (a[4] & a[6] & a[7] & a[8]) | (a[3] & a[6] & a[7] & a[8]) | (a[6] & (~a[7]) & (~a[8]));
|
|
assign y[9] = (a[0] & (~a[3]) & (~a[4]) & a[7] & a[6]) | (a[3] & a[6] & (~a[7]) & a[8]) | (a[0] & a[7] & (~a[8]) & a[6]) | (a[7] & (~a[6]));
|
|
assign y[10] = (a[1] & (~a[3]) & (~a[4]) & a[6] & a[7]) | (a[4] & a[6] & (~a[7]) & a[8]) | (a[1] & a[6] & a[7] & (~a[8])) | (a[8] & (~a[6]));
|
|
assign y[11] = a[9];
|
|
|
|
endmodule
|