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207 lines
7.8 KiB
Verilog
207 lines
7.8 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU Adder
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module xu_alu_add
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(
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//-------------------------------------------------------------------
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// Clocks & Power
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//-------------------------------------------------------------------
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input [0:`NCLK_WIDTH-1] nclk,
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inout vdd,
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inout gnd,
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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//-------------------------------------------------------------------
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// Decode Interface
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//-------------------------------------------------------------------
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input ex1_act,
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input ex2_msb_64b_sel,
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input [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv,
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input dec_alu_ex2_add_ci,
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//-------------------------------------------------------------------
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// Bypass Interface
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//-------------------------------------------------------------------
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input [64-`GPR_WIDTH:63] ex2_rs1,
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input [64-`GPR_WIDTH:63] ex2_rs2,
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//-------------------------------------------------------------------
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// Target Data
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//-------------------------------------------------------------------
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(* NO_MODIFICATION="TRUE" *) // ex2_add_rt
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// NET_DATA="PLANES=/C1 C2/" // ex2_add_rt
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output [64-`GPR_WIDTH:63] ex2_add_rt, // Add result
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(* NO_MODIFICATION="TRUE" *) // ex2_add_ovf
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output ex2_add_ovf, // Add overflow
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// Add carry
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output ex2_add_ca
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);
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localparam msb = 64-`GPR_WIDTH;
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// Latches
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wire [64-`GPR_WIDTH:63] ex2_rs1_inv_b_q; //input=>ex1_rs1_inv, act=>ex1_act
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wire [64-`GPR_WIDTH:63] ex1_rs1_inv;
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// Scanchain
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localparam ex2_rs1_inv_b_offset = 0;
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localparam scan_right = ex2_rs1_inv_b_offset + `GPR_WIDTH;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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// Signals
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wire [0:`NCLK_WIDTH-1] ex1_rs0_inv_lclk;
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wire ex1_rs0_inv_d1clk;
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wire ex1_rs0_inv_d2clk;
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wire [64-`GPR_WIDTH:63] ex2_rs1_b;
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wire [64-`GPR_WIDTH:63] ex2_rs2_b;
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wire [64-`GPR_WIDTH:63] ex2_x_b;
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wire [64-`GPR_WIDTH:63] ex2_y;
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wire [64-`GPR_WIDTH:63] ex2_y_b;
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wire ex2_aop_00;
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wire ex2_aop_32;
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wire ex2_bop_00;
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wire ex2_bop_32;
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(* NO_MODIFICATION="TRUE" *) // ex2_sgn00_32
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wire ex2_sgn00_32;
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wire ex2_sgn11_32;
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(* NO_MODIFICATION="TRUE" *) // ex2_sgn00_64
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wire ex2_sgn00_64;
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wire ex2_sgn11_64;
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wire ex2_cout_32;
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wire ex2_cout_00;
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(* NO_MODIFICATION="TRUE" *) // ex2_ovf32_00_b
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wire ex2_ovf32_00_b;
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wire ex2_ovf32_11_b;
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(* NO_MODIFICATION="TRUE" *) // ex2_ovf64_00_b
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wire ex2_ovf64_00_b;
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wire ex2_ovf64_11_b;
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wire [64-`GPR_WIDTH:63] ex2_add_rslt;
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wire [64-`GPR_WIDTH:63] ex2_rs1_inv_q;
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generate
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genvar i;
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for (i=0; i<`GPR_WIDTH; i=i+1) begin : ex1_rs1_inv_gen
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assign ex1_rs1_inv[i] = dec_alu_ex1_add_rs1_inv[i % (`GPR_WIDTH/8)];
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end
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endgenerate
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assign ex2_rs1_inv_q = (~ex2_rs1_inv_b_q);
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assign ex2_rs1_b = (~ex2_rs1);
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assign ex2_rs2_b = (~ex2_rs2);
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assign ex2_x_b = ex2_rs1_b ^ ex2_rs1_inv_q; // xor2_x2m --w=12
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assign ex2_y = (~ex2_rs2_b); // inv_x1m --w=4
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assign ex2_y_b = (~ex2_y); // inv_x2m --w=4
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assign ex2_aop_00 = (~ex2_x_b[msb]);
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assign ex2_aop_32 = (~ex2_x_b[32]);
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assign ex2_bop_00 = (~ex2_y_b[msb]);
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assign ex2_bop_32 = (~ex2_y_b[32]);
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tri_st_add csa(
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.x_b(ex2_x_b),
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.y_b(ex2_y_b),
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.ci(dec_alu_ex2_add_ci),
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.sum(ex2_add_rslt),
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.cout_32(ex2_cout_32),
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.cout_0(ex2_cout_00)
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);
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assign ex2_add_rt = ex2_add_rslt;
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// Overflow occurs when the sign bit of the inputs differs from the sign of the result
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assign ex2_sgn00_32 = (~ex2_msb_64b_sel) & (~ex2_aop_32) & (~ex2_bop_32);
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assign ex2_sgn11_32 = (~ex2_msb_64b_sel) & ex2_aop_32 & ex2_bop_32;
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assign ex2_sgn00_64 = ex2_msb_64b_sel & (~ex2_aop_00) & (~ex2_bop_00);
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assign ex2_sgn11_64 = ex2_msb_64b_sel & ex2_aop_00 & ex2_bop_00;
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assign ex2_ovf32_00_b = (~(ex2_add_rslt[32] & ex2_sgn00_32));
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assign ex2_ovf32_11_b = (~((~ex2_add_rslt[32]) & ex2_sgn11_32));
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assign ex2_ovf64_00_b = (~(ex2_add_rslt[msb] & ex2_sgn00_64));
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assign ex2_ovf64_11_b = (~((~ex2_add_rslt[msb]) & ex2_sgn11_64));
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assign ex2_add_ovf = (~(ex2_ovf64_00_b & ex2_ovf64_11_b & ex2_ovf32_00_b & ex2_ovf32_11_b));
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//-------------------------------------------------------------------
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// Latch instances
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//-------------------------------------------------------------------
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assign ex2_add_ca = (ex2_msb_64b_sel == 1'b1) ? ex2_cout_00 : ex2_cout_32;
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tri_lcbnd ex1_rs0_inv_lcb(
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.vd(vdd),
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.gd(gnd),
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.act(ex1_act),
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.nclk(nclk),
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.force_t(func_sl_force),
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.thold_b(func_sl_thold_0_b),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.sg(sg_0),
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.lclk(ex1_rs0_inv_lclk),
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.d1clk(ex1_rs0_inv_d1clk),
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.d2clk(ex1_rs0_inv_d2clk)
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);
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tri_inv_nlats #(.WIDTH(`GPR_WIDTH), .BTR("NLI0001_X1_A12TH"), .INIT(0)) ex1_rs0_inv_b_latch(
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.vd(vdd),
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.gd(gnd),
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.lclk(ex1_rs0_inv_lclk),
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.d1clk(ex1_rs0_inv_d1clk),
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.d2clk(ex1_rs0_inv_d2clk),
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.scanin(siv[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]),
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.scanout(sov[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]),
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.d(ex1_rs1_inv),
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.qb(ex2_rs1_inv_b_q)
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);
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assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
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assign scan_out = sov[0];
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endmodule
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