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90 lines
3.1 KiB
Markdown
90 lines
3.1 KiB
Markdown
# Verilator
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### core-only initial experiment - used to work
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims c.v tb.cpp
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make -C obj_dir -f Vc.mk Vc
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obj_dir/Vc
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```
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### core + node (extmem version)
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims -Iverilog/a2node a2owb.v tb_node.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* doesn't work (test3/mem.init), which does work for coccotb/icarus
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* tid compare at start looks like it's using wrong value (imm from following bc?) and erat code is skipped
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### core + node (extmem version) with cg disabled
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* add inits for iucr0, xucr0, mmucr2 to disable controllable clk gating to verilog/clkgating
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/clkgating -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims -Iverilog/a2node a2owb.v tb_node.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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### core + node (extmem version) with cg disabled, test, etc. inputs tied in a2owb.v to optimize out
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* verilog/a2onode_verilator
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/clkgating -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims -Iverilog/a2node_verilator a2owb.v tb_node.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* nothing fixed it yet; comparing wave with coco, rv is issuing ops/itags in different order; renaming must be messed up because seems like the thread compare is using the r0 from the erat setup (1F) after the branch (getting nonzero compare and branching)
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```
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00000400 <boot_start>:
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400: 7c be 6a a6 mfspr r5,446
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404: 2c 25 00 00 cmpdi r5,0
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408: 40 82 00 e0 bne 4e8 <init_t123>
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40c: 3c 60 8c 00 lis r3,-29696
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410: 38 00 00 1f li r0,31
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414: 38 40 00 15 li r2,21
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418: 38 80 00 00 li r4,0
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41c: 39 00 02 3f li r8,575
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```
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* doesn't occur with cocotb with normal credits or 1-only credit
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* cleaned up many UNOPTFLATs
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* go back to 'normal' (no clkgating disable); also enable BP since it was disabled from original test
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 --timescale 1ns/1ns --report-unoptflat -Wno-fatal -Wno-PINMISSING -Wno-WIDTH -Wno-LITENDIAN --error-limit 1 -Iverilog/a2node_verilator -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims -Iverilog/work a2owb.v tb_node.cpp 2>&1 | tee verilator.txt
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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### core + node wb (litex)
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* verilog/a2onode_litex
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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