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155 lines
5.1 KiB
Markdown
155 lines
5.1 KiB
Markdown
# Verilator
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### core-only initial experiment
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims c.v tb.cpp
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make -C obj_dir -f Vc.mk Vc
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obj_dir/Vc
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```
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### core + node (extmem version)
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims -Iverilog/a2node a2owb.v tb_node.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* doesn't work (test3/mem.init), which does work for coccotb/icarus
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* tid compare at start looks like it's using wrong value (imm from following bc?) and erat code is skipped
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### core + node wb (litex)
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* verilog/a2onode_litex
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* debugged several fails near start of test (in issues) - first few are cases of ff behaving incorrectly; syntax changes in trilib got to reaching i=1 ifetches
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* added CP signals to track completions (/*verilator public*/) and now first isync fails (flushes to @04)
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# Verilator Debug
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* verilator now successfully runs, once the nclk[] changes were completed to separate clk and rst, and
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remove lcb's driving lclk's
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp |& tee verilator.txt
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```
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* about 5 non-scan UNOPTFLATs
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##### Old Stuff
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* install multiple versions concurrently
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```
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git pull
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git checkout master
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#..or...
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#git checkout stable
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#git checkout vxxx
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unset VERILATOR_ROOT
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export VERILATOR_VERSION=`git describe | sed "s/verilator_//"`
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./configure --prefix /tools/verilator/$VERILATOR_VERSION
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make -j <n>
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make install
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cp -r include /tools/verilator/$VERILATOR_VERSION # had to do this too
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# symlink
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ln -sf /tools/verilator/$VERILATOR_VERSION /tools/verilator/latest
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```
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* pick and run...
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```
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export VERILATOR_ROOT=/tools/verilator/latest
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# rm -r obj_dir # to be safe?
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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#### Try different versions with same RTL
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* rtl and tb_litex.cpp
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```
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git log | head -1
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commit 7cbbf9f3844a9287c5fac88867bcbcd5739914cf
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```
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* export VERILATOR_ROOT=/tools/verilator/v4.106
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* #define OLD_PUBLIC in tb_litex.cpp
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* the ifetch is bad, but so are the completes a little before it; @42C=```eratwe r8,r0,0```
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...
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00000250 Completed: I0:1 000000000000042C
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00000262 WB RD RA=00000460
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00000263 WB RD ACK RA=00000460 DATA=7D4011A6
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00000264 WB RD RA=00000464
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00000265 WB RD ACK RA=00000464 DATA=7C8009A6
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00000266 WB RD RA=00000468
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00000267 WB RD ACK RA=00000468 DATA=7D0001A6
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00000268 WB RD RA=0000046C
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00000269 WB RD ACK RA=0000046C DATA=4C00012C
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00000272 Completed: I0:1 0000000000000000 I1:1 0000000000000000
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00000286 WB RD RA=00000000
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*** Fetch to boot address (00000000) after initial boot! ***
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```
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* export VERILATOR_ROOT=/tools/verilator/v4.204
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```
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00000250 Completed: I0:1 000000000000042C
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00000262 WB RD RA=00000460
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00000263 WB RD ACK RA=00000460 DATA=7D4011A6
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00000264 WB RD RA=00000464
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00000265 WB RD ACK RA=00000464 DATA=7C8009A6
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00000266 WB RD RA=00000468
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00000267 WB RD ACK RA=00000468 DATA=7D0001A6
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00000268 WB RD RA=0000046C
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00000269 WB RD ACK RA=0000046C DATA=4C00012C
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00000272 Completed: I0:1 0000000000000000 I1:1 0000000000000000
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00000286 WB RD RA=00000000
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*** Fetch to boot address (00000000) after initial boot! ***
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...
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* export VERILATOR_ROOT=/tools/verilator/stable (v4.224-26-g8b7480806)
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```
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00000250 Completed: I0:1 000000000000042C
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00000262 WB RD RA=00000460
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00000263 WB RD ACK RA=00000460 DATA=7D4011A6
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00000264 WB RD RA=00000464
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00000265 WB RD ACK RA=00000464 DATA=7C8009A6
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00000266 WB RD RA=00000468
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00000267 WB RD ACK RA=00000468 DATA=7D0001A6
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00000268 WB RD RA=0000046C
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00000269 WB RD ACK RA=0000046C DATA=4C00012C
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00000272 Completed: I0:1 0000000000000000 I1:1 0000000000000000
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00000286 WB RD RA=00000000
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*** Fetch to boot address (00000000) after initial boot! ***
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```
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* export VERILATOR_ROOT=/tools/verilator/latest (v4.224-82-gcbe1b8e26)
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```
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%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt
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%Error: Command Failed /tools/verilator/latest/bin/verilator_bin -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -I
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verilator -cc --debug --gddbt--exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp |& tee verilator-v224-82-debug.txt
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```
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