You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
openpowerwtf c82f7a3330 add wishbone interface 2 years ago
..
build_smt2 add dev 2 years ago
build_st init 2 years ago
build_sweetpea add dev 2 years ago
A2L2.py add wishbone interface 2 years ago
A2O.py hang detect 2 years ago
Makefile.node add wishbone interface 2 years ago
Makefile.smt2 init 2 years ago
Makefile.st random tst, bios 2 years ago
Makefile.sweetpea add dev 2 years ago
Makefile.verilator add dev 2 years ago
Makefile.wb add wishbone interface 2 years ago
OPEnv.py add wishbone interface 2 years ago
boot.lst add dev 2 years ago
cocotb_icarus.v add dev 2 years ago
cocotb_icarus_node.v tie pervasive sigs in rtl 2 years ago
makegtkw add dev 2 years ago
pyvcd.gtkw add dev 2 years ago
readme.md add wishbone interface 2 years ago
results.xml init 2 years ago
sim.png add dev 2 years ago
sim.txt runs test3 2 years ago
tb.py add wishbone interface 2 years ago
tb_node.py add wishbone interface 2 years ago
verilog add dev 2 years ago
wtf.gtkw random tst, bios 2 years ago

readme.md

Cocotb Sim Experiments

Core-only version with partial implementation of Python A2L2 interface

  • testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac

Core+wrapper version with partial implementation of A2Node (direct memory)

  • testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac

Core+wrapper version with implementation of A2Node (Wishbone system bus)

  • testbench provides 4B Wishbone memory interface (using cocoext-wishbone for now)
make -f Makefile.wb build |& grep -v Anac
``

* update wrapper to include normal Litex, etc. I/O (WB plus ints, config, etc.)
* add Litex core definition (migen)

* can add L2 mem
* can add multiple core intefaces (SMP)
* can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)