The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
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openpowerwtf d2901c3177 update 10 months ago
synth update 10 months ago update 10 months ago


  • for source experiments (parameters, etc. to change core gen), and other source updates for PD

minimize cache/queues/etc. for eFabless

  • the parameters were likely not tested much, and may have dependencies, etc.
  • see which ones can change and still compile/run simple test; document dependencies

test OpenROAD tools

  1. try unit/sub-unit synthesis and static timing, using blackbox arrays amd estimated wiring for some pdk (nangate45?)

    • equivalent to a CI timing script to catch functional changes that break timing
  • what are the OR steps to do this? can this be done with only yosys script?s

    • floorplan - unbounded?
    • pins - no placement if no bounds, and relaxed i/o assertions?
    • tap cells/power dist/etc. - not needed (account for in estimated wiring?)
    • clock tree synthesis - no (assume ideal clocks + fudge)
    • iterate
      • placement
      • cap/slew/fo checks
      • setup/hold
  • are results consistent with expected cycle time?


  • blackbox arrays
cd synth
yosys -s synth.yo


git clone --recursive
cd OpenROAD-flow-scripts
./ [--threads n]
docker run -it -u $(id -u ${USER}):$(id -g ${USER}) -v $(pwd)/flow/platforms:/OpenROAD-flow-scripts/flow/platforms:ro openroad/flow-scripts