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src/verilog/trilib src/verilog/work src/vhdl
build bd (project) ip_cache (empty until project built) ip_repo (empty until IP built/copied) ip_user (IP macros to be built) tcl (build scripts)
doc core user guide, etc.
IP is created in ip_user and copied to ip_repo for use in top level bd.
Simple card components:
Help Vivado attach to VIO correctly:
reverserator_3 reverserator_4 reverserator_64
- create project