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95 lines
2.3 KiB
Markdown
95 lines
2.3 KiB
Markdown
2 years ago
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# Magic Incantations for Litex Integration
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## Litex General
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### add local platform
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from platforms import cmod7
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### add local core
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```
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binPath = os.path.dirname(os.path.realpath(__file__))
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sys.path.append(os.path.join(binPath, 'a2p'))
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from a2p import A2P
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from litex.soc.cores import cpu
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cpu.CPUS['a2p'] = A2P
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```
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### add local modules
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```
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sys.path.append(os.path.join(binPath, 'modules'))
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```
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### add extra UARTs (GPIO)
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* must add PHY and UART to CSR
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```
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self.submodules.uart_1_phy = RS232PHY(pins, sys_clk_freq, 115200, with_dynamic_baudrate=True)
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self.add_csr('uart_1_phy')
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self.submodules.uart_1 = UART(phy=self.uart_1_phy)
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self.add_csr('uart_1')
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```
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* dynamic baudrate allows setting it in csr
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* tuning_word = int((baudrate/clk_freq)*2**32)
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* in bios
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* ```#define CONFIG_CLOCK_FREQUENCY 100000000```
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* or read freq with config_clock_frequency_read()
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* access csr with generated UART_1 funcs
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* 115200=004B7F5A (4947802)
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* 9600=00064A9C (412316)
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### add 'CSR Definition' CSR for indirectly addressing CSRs, so that code doesn't need to change when gateware rebuilt
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* add a 'CSR Definition' region at constant location (like CSR_BASE)
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* contains list of CSRs which point to and define CSRs available
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* Base Addr: 24 bits, Identifier: 8 bits
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* also could self.add_constant(ID) for each, so that software can use constants to check Identifier
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* needs to be able to reserve its region, then find out what's been built and add its regs before finalize()
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### allow lxterm and lxserver to share main uart (crossover)
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## Litex RTL
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### add verilog module to top, between top-level bus and I/Os (slave)
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```
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from issiram import ISSIRam
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platform.add_source("./modules/issiram.v")
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sram_bus = wishbone.Interface()
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pins = platform.request('issiram')
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# to rename pins
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mem = {
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'ce': pins.cen,
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'oe': pins.oen,
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'we': pins.wen,
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'adr': pins.addr,
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'dat': pins.data
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}
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sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, mem)
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self.submodules.sram = sram
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self.bus.add_slave('sram', sram_bus, SoCRegion(origin=self.mem_map['sram'], size=sram.size))
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self.logger.info("SRAM {} {} {}.".format(
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colorer('sram'),
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colorer("added", color="green"),
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self.bus.regions['sram'])
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)
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```
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### add verilog module to top, with connections to other top-level signals
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### add Litex L2 between WB and verilog module
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