init bridge/smp stuff
wtf
3 years ago
parent
8b01139c2d
commit
4a8aeab3be
@ -0,0 +1,274 @@
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// A2 Core Bridge
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// should modularize as much as possible and just do messy rewiring here!
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// one thread/core for now
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// possible extended command modifiers
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// prefetch
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// larx
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// stcx
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// lwsync
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// hwsync
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// tlbsync
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// ici, icbi
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// dci, dcbi, etc
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// dcbtst
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// dcbz
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// tlbie, etc
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// possible extended responses
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// errors
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// crit first, xfer# for larger bus width on core side
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// credits
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// resv valid
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// stcx comp/pass
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// sync ack
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// back inv val/addr
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// possible extra functions
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// integrated L2
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// doorbell/mailbox (peer/broadcast msg/rsp/intr side channel crossbar)
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// cores must be contiguous, starting at 0
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`define CORE_TYPE_NONE 4'h0
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`define CORE_TYPE_A2L2 4'h1
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`define CORE_TYPE_WB1 4'h2
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`define CORE_TYPE_WB2 4'h3
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`define BUS_TYPE_NONE 4'h0
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`define BUS_TYPE_WB1 4'h1
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`define BUS_TYPE_WB2 4'h2
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module A2WB #(
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parameter [0:15] CORE_TYPES = {`CORE_TYPE_WB2, `CORE_TYPE_NONE, `CORE_TYPE_NONE, `CORE_TYPE_NONE},
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parameter [0:3] BUS_TYPE = `BUS_TYPE_WB2
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) (
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input clk,
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input rst,
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input [0:3] core_in,
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output [0:3] core_out,
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input bus_in,
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output bus_out
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);
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integer NUMCORES = 0;
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genvar i;
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// ------------------------------------------------------------------------------------------------
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// I/O Connections
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wire i_wb_cyc [0:3];
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wire i_wb_stb [0:3];
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wire [31:2] i_wb_adr[0:3] ;
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wire i_wb_ack [0:3];
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wire [31:0] i_wb_datr[0:3];
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wire d_wb_cyc [0:3];
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wire d_wb_stb [0:3];
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wire d_wb_we [0:3];
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wire [3:0] d_wb_sel [0:3];
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wire [31:0] d_wb_adr [0:3];
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wire [31:0] d_wb_datw [0:3];
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wire d_wb_ack [0:3];
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wire [31:0] d_wb_datr[0:3];
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wire [7:0] ext_cmd [0:3];
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wire [7:0] ext_rsp [0:3];
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generate
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for (i = 0; i < 4; i++) begin
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case (CORE_TYPES[i*4:i*4+3])
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4'h0: begin
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end
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4'h1: begin
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assign NUMCORES = NUMCORES + 1;
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// a2l2
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end
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4'h2: begin
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assign NUMCORES = NUMCORES + 1;
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wire [78:0] core_0_in;
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wire [32:0] core_out[i];
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assign d_wb_cyc[i] = core_in[i][78];
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assign d_wb_stb[i] = core_in[i][77];
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assign d_wb_we[i] = core_in[i][76];
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assign d_wb_sel[i] = core_in[i][75:72];
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assign d_wb_adr[i] = core_in[i][71:40];
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assign d_wb_datw[i] = core_in[i][39:8];
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assign ext_cmd[i] = core_in[i][7:0];
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assign core_out[i][32] = d_wb_ack[i];
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assign core_out[i][31:0] = d_wb_datr[i];
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end
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4'h3: begin
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assign NUMCORES = NUMCORES + 1;
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wire [110:0] core_in[i];
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wire [65:0] core_out[i];
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assign i_wb_cyc[i] = core_in[i][110];
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assign i_wb_stb[i] = core_in[i][109];
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assign i_wb_adr[i] = core_in[i][108:79];
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assign d_wb_cyc[i] = core_in[i][78];
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assign d_wb_stb[i] = core_in[i][77];
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assign d_wb_we[i] = core_in[i][76];
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assign d_wb_sel[i] = core_in[i][75:72];
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assign d_wb_adr[i] = core_in[i][71:40];
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assign d_wb_datw[i] = core_in[i][39:8];
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assign ext_cmd[i] = core_in[i][7:0];
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assign core_out[i][65] = i_wb_ack[i];
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assign core_out[i][64:33] = i_wb_datr[i];
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assign core_out[i][32] = d_wb_ack[i];
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assign core_out[i][31:0] = d_wb_datr[i];
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end
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endcase
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Command Queues/Addr Compare/Bypass
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//
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// cores can have either 1 or 2 buses; assume single-cmd outstanding per, for now
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// a2l2 could also allow 1 ld, 1 st credit and use 2 dedicated queues
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reg [77:0] cmd_queue_q[0:3][0:1];
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wire [77:0] cmd_queue_d[0:3][0:1];
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wire [77:0] cmd_queue_in[0:3][0:1];
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wire [71:0] cmd_queue_out[0:3];
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generate
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for (i = 0; i < 4; i++) begin
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case (CORE_TYPES[i*4:i*4+3])
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4'h0: begin
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end
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4'h1: begin
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// convert a2l2 to internal format
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end
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4'h2: begin
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// q[0] = i or d
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assign cmd_queue_in[i][0][77] = d_wb_cyc[i] & d_wb_stb[i]; // valid
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assign cmd_queue_in[i][0][76] = d_wb_we[i];
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assign cmd_queue_in[i][0][75:72] = d_wb_sel[i];
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assign cmd_queue_in[i][0][71:40] = d_wb_adr[i];
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assign cmd_queue_in[i][0][39:8] = d_wb_datw[i];
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assign cmd_queue_in[i][0][7:0] = ext_cmd[i];
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end
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4'h3: begin
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// q[0]=i, q[1]=d
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assign cmd_queue_in[i][0][77] = i_wb_cyc[i] & i_wb_stb[i]; // valid
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assign cmd_queue_in[i][0][76] = 'b0;
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assign cmd_queue_in[i][0][75:72] = 'b0000;
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assign cmd_queue_in[i][0][71:40] = d_wb_adr[i];
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assign cmd_queue_in[i][0][39:8] = 'h000000;
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assign cmd_queue_in[i][0][7:0] = ext_cmd[i];
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assign cmd_queue_in[i][0][77] = d_wb_cyc[i] & d_wb_stb[i]; // valid
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assign cmd_queue_in[i][0][76] = d_wb_we[i];
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assign cmd_queue_in[i][0][75:72] = d_wb_sel[i];
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assign cmd_queue_in[i][0][71:40] = d_wb_adr[i];
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assign cmd_queue_in[i][0][39:8] = d_wb_datw[i];
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assign cmd_queue_in[i][0][7:0] = ext_cmd[i];
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end
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endcase
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// SMP
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// larx/stcx
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// assume: if larx hits L1, core invalidates line automatically -> do not need to send back-invalidate
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// reservation granule is 32B (or use lcd of all cores)
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// one reservation per thread
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// reservation is set before core receives reload data
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wire stcx_store [0:3];
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wire resv_ra_hit [0:3];
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wire resv_set [0:3];
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wire resv_rst [0:3];
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wire [27:0] resv_q [0:3]; // v, @31:5
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wire [27:0] resv_d [0:3];
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// sync ack
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// cache ops
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// tlb ops
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// ------------------------------------------------------------------------------------------------
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// Arbitration
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//
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// LRU, etc. select from pending cmds
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Bus Out
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generate
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if (BUS_TYPE == `BUS_TYPE_WB1) begin
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end else if (BUS_TYPE == `BUS_TYPE_WB2) begin
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wire [101:0] bus_out;
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wire bus_i_wb_stb;
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assign bus_out[101] = bus_i_wb_stb;
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wire [31:2] bus_i_wb_adr;
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assign bus_out[100:71] = bus_i_wb_adr;
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wire bus_d_wb_cyc;
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assign bus_out[70] = bus_d_wb_cyc;
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wire bus_d_wb_stb;
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assign bus_out[69] = bus_d_wb_stb;
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wire bus_d_wb_we;
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assign bus_out[68] = bus_d_wb_we;
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wire [3:0] bus_d_wb_sel;
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assign bus_out[67:64] = bus_d_wb_sel;
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wire [31:0] bus_d_wb_adr;
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assign bus_out[63:32] = bus_d_wb_adr;
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wire [31:0] bus_d_wb_datw;
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assign bus_out[31:0] = bus_d_wb_datw;
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end else begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Bus In
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generate
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if (BUS_TYPE == `BUS_TYPE_WB1) begin
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end else if (BUS_TYPE == `BUS_TYPE_WB2) begin
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wire [65:0] bus_in;
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wire bus_i_wb_ack = bus_in[65];
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wire [31:0] bus_i_wb_datr = bus_in[64:33];
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wire bus_d_wb_ack = bus_in[32];
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wire [31:0] bus_d_wb_datr = bus_in[31:0];
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end else begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Response Queues
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Misc/Errors/Debug
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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endmodule
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@ -1 +1,36 @@
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# Bridge A2I/A2O memory interface to WB
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# A2 Interfaces to WB
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* core interfaces
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* A2I/A2O A2L2 bus
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* Single (combined I/D) w/SMP extensions
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* Dual (separate I/D) WB buses w/SMP extensions
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* bus interface
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* WB (non-SMP)
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* functions
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* arbitrates for WB bus
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* queues one or more core commands
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* point of coherncy for larx/stcx, sync, tlbie, etc. for multicores below it (single/mulithread)
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* address compares necessary for ordering/coherency
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* optional mailbox interface for core-core peer and broadcast
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## Possible configurations
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* one core, WB: pass-through with SMP functions
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* one core, A2L2: bridge with SMP functions
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* multi-core: bridge for A2L2, queueing, arbitration, and SMP functions
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@ -1,18 +0,0 @@
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# L2 Multicore
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* Multicore bridge to WB
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* generate 1-4 core interfaces (possibly mixed)
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* slave WB-I, slave WB-D, OPMC extension (opcode/WIMG/...)
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* a2i/a2o out-of-order/credits/... style
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* configurable load and store queues per interface (if pipelined/credited interfaces)
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* point-of-coherency/snoop/sync/... logic
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* configurable-size shared L2 (extra tags for pinning, etc.?)
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* WB-I, WB-D master
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@ -0,0 +1,94 @@
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# Magic Incantations for Litex Integration
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## Litex General
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### add local platform
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from platforms import cmod7
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### add local core
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```
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binPath = os.path.dirname(os.path.realpath(__file__))
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sys.path.append(os.path.join(binPath, 'a2p'))
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from a2p import A2P
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from litex.soc.cores import cpu
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cpu.CPUS['a2p'] = A2P
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```
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### add local modules
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```
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sys.path.append(os.path.join(binPath, 'modules'))
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```
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### add extra UARTs (GPIO)
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* must add PHY and UART to CSR
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```
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self.submodules.uart_1_phy = RS232PHY(pins, sys_clk_freq, 115200, with_dynamic_baudrate=True)
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self.add_csr('uart_1_phy')
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self.submodules.uart_1 = UART(phy=self.uart_1_phy)
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self.add_csr('uart_1')
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```
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* dynamic baudrate allows setting it in csr
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* tuning_word = int((baudrate/clk_freq)*2**32)
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* in bios
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* ```#define CONFIG_CLOCK_FREQUENCY 100000000```
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* or read freq with config_clock_frequency_read()
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* access csr with generated UART_1 funcs
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* 115200=004B7F5A (4947802)
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* 9600=00064A9C (412316)
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### add 'CSR Definition' CSR for indirectly addressing CSRs, so that code doesn't need to change when gateware rebuilt
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* add a 'CSR Definition' region at constant location (like CSR_BASE)
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* contains list of CSRs which point to and define CSRs available
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* Base Addr: 24 bits, Identifier: 8 bits
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* also could self.add_constant(ID) for each, so that software can use constants to check Identifier
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* needs to be able to reserve its region, then find out what's been built and add its regs before finalize()
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### allow lxterm and lxserver to share main uart (crossover)
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## Litex RTL
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### add verilog module to top, between top-level bus and I/Os (slave)
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```
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from issiram import ISSIRam
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platform.add_source("./modules/issiram.v")
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sram_bus = wishbone.Interface()
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pins = platform.request('issiram')
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# to rename pins
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mem = {
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'ce': pins.cen,
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'oe': pins.oen,
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'we': pins.wen,
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'adr': pins.addr,
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'dat': pins.data
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}
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sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, mem)
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self.submodules.sram = sram
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self.bus.add_slave('sram', sram_bus, SoCRegion(origin=self.mem_map['sram'], size=sram.size))
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self.logger.info("SRAM {} {} {}.".format(
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colorer('sram'),
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colorer("added", color="green"),
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self.bus.regions['sram'])
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)
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```
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### add verilog module to top, with connections to other top-level signals
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### add Litex L2 between WB and verilog module
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