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      rtl/l2mc/readme.md
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rtl/l2mc/readme.md

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# L2 Multicore

* WB bridge for multiple cores

* generate 1-4 core interfaces (slave WB-I, slave WB-D, OPMC extension (opcode/WIMG/...))

* configurable load and store queues per interface (if pipelined buses)

* point-of-coherency/snoop/sync/... logic

* configurable-size shared L2 (extra tags for pinning, etc.?)

* WB-I, WB-D master

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rtl/nianalyzer/.mt

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# NIAnalyzer

## Programmable NIA analyzer and debugger

Receives debug bus (NIA, val, advancing, count, tag bits) and counts various events:

* compare NIA vs all block specs (start/end) to match one or more blocks, or none (also counted)
* count 'advancing' (count is for multiple completions)
* could count 'valid and not advancing' cycles (latency); may only make sense for single ops
* tag bits could specify b/alu/rot/ld/st/spec/etc. or other info (icmiss, dcmiss, stall, byps, ...)
* could also be able to generate signal(s) based on events (stall/interrupt core when full), event seen, etc.


* gen-configurable

* nia width, number of buckets, ...
* local bram size

* csr-configurable

* buckets def
* ctls (start/stop/rst/...)

* wb interface to connect to uart/eth/mem


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