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L2 Multicore

WB bridge for multiple cores
- generate 1-4 core interfaces (slave WB-I, slave WB-D, OPMC extension (opcode/WIMG/...))
- configurable load and store queues per interface (if pipelined buses)
- point-of-coherency/snoop/sync/... logic
- configurable-size shared L2 (extra tags for pinning, etc.?)
- WB-I, WB-D master