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simple test

master
wtf 1 year ago
parent
commit
32586292a4
  1. 183
      software/arci/arcigen.py
  2. 282
      software/arci/arcitst.tpl
  3. 26
      software/arci/simple.tst

183
software/arci/arcigen.py

@ -35,10 +35,12 @@ licenses for the specific Power ISA Core are granted under this modified Apache @@ -35,10 +35,12 @@ licenses for the specific Power ISA Core are granted under this modified Apache
"""

from types import MethodType
from ctypes import c_uint32
from string import Template
import time
from ctypes import c_uint32

# set up
# -------------------------------------------------------------------------------------------------
# Initialization

header = """
* arci v.0.0001
@ -47,13 +49,27 @@ header = """ @@ -47,13 +49,27 @@ header = """
header += f'* Generated: {time.strftime("%b %d %Y %I:%M:%S %p %Z", time.gmtime())}\n'
header += '*\n'

magic = "0x08675309"
savespr = "tar"

tplFileAsm = 'arcitst.tpl'
tstName = 'simple'
outFileTst = f'{tstName}.tst'
outFileAsm = f'{tstName}.s'

# -------------------------------------------------------------------------------------------------
# Process command line


# -------------------------------------------------------------------------------------------------
# Classes

class Fac:

def __init__(self, name, value=None, spr=False, gpr=False, fpr=False, vsr=False):
def __init__(self, name, value=None, spr=False, gpr=False, fpr=False, vsr=False, rname=None):
self.name = name
self.rname = name if rname is None else rname
self.init = value
self.value = value
self.spr = spr
self.gpr = gpr
@ -67,7 +83,7 @@ class Fac: @@ -67,7 +83,7 @@ class Fac:
return ''

def print(self):
lines.append(f'R {self.name:6} {self.value:08X}')
lines.append(f'R {self.rname:6} {self.value:08X}')


class Op:
@ -85,6 +101,11 @@ class Op: @@ -85,6 +101,11 @@ class Op:
v = 0xFFFF0000 + v
return v

# has to also keep addresses since tst can be sparse when branching (to gen'd label)
def addToStream(self):
ops.append(self.op)


# probs make different Op versions for different formats
class Addi(Op):

@ -96,7 +117,7 @@ class Addi(Op): @@ -96,7 +117,7 @@ class Addi(Op):
self.ra = ra
self.imm = v
v = self.se16(v)
if ra == "R00":
if ra == 'r0':
res = c_uint32(v).value
else:
res = c_uint32(c_uint32(gpr[ra].value).value + v).value
@ -104,15 +125,17 @@ class Addi(Op): @@ -104,15 +125,17 @@ class Addi(Op):
self.cia = cia.value
cia.value += 4
self.nia = cia.value
if ra != "R00":
if ra != 'r0':
gpr[ra].ref = True
gpr[rt].chg = True
cia.chg = True
self.res = [(rt, gpr[rt].value, gpr[rt].comment()),(cia.name, self.nia, cia.comment())]
self.op = f'{self.name:10s} {self.rt},{self.ra},{self.imm}'
self.res = [(gpr[rt].rname, gpr[rt].value, gpr[rt].comment()),(cia.rname, self.nia, cia.comment())]
return self

def print(self):
lines.append(f'I {self.cia:08X} {self.name:10s} {self.rt},{self.ra},{self.imm}')
self.addToStream()
lines.append(f'I {self.cia:08X} {self.op}')
for i in range(len(self.res)):
lines.append(f'R {self.res[i][0]:6} {self.res[i][1]:08X} {self.res[i][2]}')
lines.append('')
@ -136,11 +159,12 @@ class Add(Op): @@ -136,11 +159,12 @@ class Add(Op):
gpr[rb].ref = True
gpr[rt].chg = True
cia.chg = True
self.res = [(rt, gpr[rt].value, gpr[rt].comment()),(cia.name, self.nia, cia.comment())]
self.op = f'{self.name:10s} {self.rt},{self.ra},{self.rb}'
self.res = [(gpr[rt].rname, gpr[rt].value, gpr[rt].comment()),(cia.rname, self.nia, cia.comment())]
return self

def print(self):
lines.append(f'I {self.cia:08X} {self.name:10s} {self.rt},{self.ra},{self.rb}')
lines.append(f'I {self.cia:08X} {self.op}')
for i in range(len(self.res)):
lines.append(f'R {self.res[i][0]:6} {self.res[i][1]:08X} {self.res[i][2]}')
lines.append('')
@ -173,11 +197,12 @@ class Add_R(Op): @@ -173,11 +197,12 @@ class Add_R(Op):
gpr[rt].chg = True
cr.chg = True
cia.chg = True
self.res = [(rt, gpr[rt].value,gpr[rt].comment()), (cr.name, cr.value, cr.comment()), (cia.name, self.nia, cia.comment())]
self.op = f'{self.name:10s} {self.rt},{self.ra},{self.rb}'
self.res = [(gpr[rt].rname, gpr[rt].value,gpr[rt].comment()), (cr.rname, cr.value, cr.comment()), (cia.rname, self.nia, cia.comment())]
return self

def print(self):
lines.append(f'I {self.cia:08X} {self.name:10s} {self.rt},{self.ra},{self.rb}')
lines.append(f'I {self.cia:08X} {self.op}')
for i in range(len(self.res)):
lines.append(f'R {self.res[i][0]:6} {self.res[i][1]:08X} {self.res[i][2]}')
lines.append('')
@ -192,9 +217,10 @@ class Add_R(Op): @@ -192,9 +217,10 @@ class Add_R(Op):
# chg=True: print only if changed

def printSPR(all=False, ref=None, chg=None):

for k,f in facs.items():
if f.spr:
n = f.name
n = f.rname
v = f.value
c = f.comment()
if all or (v != 0 and ref is None and chg is None) or (ref is not None and f.ref == ref) or (chg is not None and f.chg == chg):
@ -202,9 +228,10 @@ def printSPR(all=False, ref=None, chg=None): @@ -202,9 +228,10 @@ def printSPR(all=False, ref=None, chg=None):


def printRegs(all=False, ref=None, chg=None):

for i in range(32):
n = f'R{i:02}'
g = gpr[n]
g = gpr[f'r{i}']
n = g.rname
v = g.value
c = g.comment()
if all or (v != 0 and ref is None and chg is None) or (ref is not None and g.ref == ref) or (chg is not None and g.chg == chg):
@ -215,12 +242,49 @@ def printTest(): @@ -215,12 +242,49 @@ def printTest():
for i in range(len(lines)):
print(lines[i])

def genAsm(tplFile, asmFile):

f = open(tplFile, 'r')
tplString = f.read()
tpl = Template(tplString)

tstData = {
'tst_name': tstName,
'tst_info': 'wtf',
'magic': magic,
'savespr': savespr
}

for k,f in facs.items():
if f.spr:
tstData[f'init_{f.rname.lower()}'] = f'0x{f.init:08X}'
tstData[f'expt_{f.rname.lower()}'] = f'0x{f.init:08X}'

for i in range(32):
v = gpr[f'r{i}'].init
tstData[f'init_r{i}'] = f'0x{v:08X}'
v = gpr[f'r{i}'].value
tstData[f'expt_r{i}'] = f'0x{v:08X}'

stream = ''
for i in range(len(ops)):
stream += f'\t\t\t{ops[i]}\n'

tstData['stream'] = stream[0:-1]

tpl = tpl.substitute(tstData)

f = open(asmFile, "w")
f.write(tpl)
f.close()


# -------------------------------------------------------------------------------------------------
# Create facs and aliases

lines = []
facs = {}
ops = {}
ops = []

cia = Fac('CIA', 0x120000, spr=True)

@ -240,52 +304,57 @@ def xerSO(self): @@ -240,52 +304,57 @@ def xerSO(self):
xer = Fac('XER', 0, spr=True)
xer.so = MethodType(xerSO, xer)

srr0 = Fac('SRR0', 0, spr=True)
srr1 = Fac('SRR1', 0, spr=True)
dar = Fac('DAR', 0, spr=True)
dsisr = Fac('DSISR',0, spr=True)
ctr = Fac('CTR', 0xF0000000, spr=True)
lr = Fac('LR', 0, spr=True)
tar = Fac('TAR', 0, spr=True)

# probs some trick
r0 = 'R00'
r1 = 'R01'
r2 = 'R02'
r3 = 'R03'
r4 = 'R04'
r5 = 'R05'
r6 = 'R06'
r7 = 'R07'
r8 = 'R08'
r9 = 'R09'
r10 = 'R10'
r11 = 'R11'
r12 = 'R12'
r13 = 'R13'
r14 = 'R14'
r15 = 'R15'
r16 = 'R16'
r17 = 'R17'
r18 = 'R18'
r19 = 'R19'
r20 = 'R20'
r21 = 'R21'
r22 = 'R22'
r23 = 'R23'
r24 = 'R24'
r25 = 'R25'
r26 = 'R26'
r27 = 'R27'
r28 = 'R28'
r29 = 'R29'
r30 = 'R30'
r31 = 'R31'
#srr0 = Fac('SRR0', 0, spr=True)
#srr1 = Fac('SRR1', 0, spr=True)
#dar = Fac('DAR', 0, spr=True)
#dsisr = Fac('DSISR',0, spr=True)

gpr = {}
# probs some trick
r0 = 'r0'
r1 = 'r1'
r2 = 'r2'
r3 = 'r3'
r4 = 'r4'
r5 = 'r5'
r6 = 'r6'
r7 = 'r7'
r8 = 'r8'
r9 = 'r9'
r10 = 'r10'
r11 = 'r11'
r12 = 'r12'
r13 = 'r13'
r14 = 'r14'
r15 = 'r15'
r16 = 'r16'
r17 = 'r17'
r18 = 'r18'
r19 = 'r19'
r20 = 'r20'
r21 = 'r21'
r22 = 'r22'
r23 = 'r23'
r24 = 'r24'
r25 = 'r25'
r26 = 'r26'
r27 = 'r27'
r28 = 'r28'
r29 = 'r29'
r30 = 'r30'
r31 = 'r31'

def commentGPR(self):
return f'* {self.value:10}'

for i in range(32):
name = f'R{i:02}'
gpr[name] = Fac(name, 0, gpr=True)
#name = f'R{i:02}'
name = f'r{i}'
gpr[name] = Fac(name, 0, gpr=True, rname=f'R{i:02}')
gpr[name].comment = MethodType(commentGPR, gpr[name])

# -------------------------------------------------------------------------------------------------
@ -323,6 +392,6 @@ printSPR(all=True) @@ -323,6 +392,6 @@ printSPR(all=True)
printRegs(all=True)

# create .tst file
printTest()
# create .s file
# create .o file (or two, one the test, one the test+runner)
printTest()
genAsm(tplFileAsm, outFileAsm)

282
software/arci/arcitst.tpl

@ -0,0 +1,282 @@ @@ -0,0 +1,282 @@
# architst

.include "defines.s"

# -------------------------------------------------------------------------------------------------
# c-accessible

.global init_tst
.global tst_inits
.global tst_results
.global tst_expects

# -------------------------------------------------------------------------------------------------
tst_misc:

tst_name: .asciz "$tst_name"
tst_info: .asciz "$tst_info"

.set SAVESPR,$savespr
.set MAGIC,$magic

# -------------------------------------------------------------------------------------------------
.align 5
tst_inits:

init_r0: .long $init_r0
init_r1: .long $init_r1
init_r2: .long $init_r2
init_r3: .long $init_r3
init_r4: .long $init_r4
init_r5: .long $init_r5
init_r6: .long $init_r6
init_r7: .long $init_r7
init_r8: .long $init_r8
init_r9: .long $init_r9
init_r10: .long $init_r10
init_r11: .long $init_r11
init_r12: .long $init_r12
init_r13: .long $init_r13
init_r14: .long $init_r14
init_r15: .long $init_r15
init_r16: .long $init_r16
init_r17: .long $init_r17
init_r18: .long $init_r18
init_r19: .long $init_r19
init_r20: .long $init_r20
init_r21: .long $init_r21
init_r22: .long $init_r22
init_r23: .long $init_r23
init_r24: .long $init_r24
init_r25: .long $init_r25
init_r26: .long $init_r26
init_r27: .long $init_r27
init_r28: .long $init_r28
init_r29: .long $init_r29
init_r30: .long $init_r30
init_r31: .long $init_r31

init_cr: .long $init_cr
init_xer: .long $init_xer
init_ctr: .long $init_ctr
init_lr: .long $init_lr
init_tar: .long $init_tar

save_r1: .long 0
save_r30: .long 0
save_r31: .long 0

# -------------------------------------------------------------------------------------------------
# r3=@tst_inits
.align 5
init_tst:

# save c stuff
stw r1,(save_r1-tst_inits)(r3)
stw r30,(save_r30-tst_inits)(r3)
stw r31,(save_r31-tst_inits)(r3)

# init test regs
lwz r1,(init_cr-tst_inits)(r3)
mtcr r1
lwz r1,(init_xer-tst_inits)(r3)
mtxer r1
lwz r1,(init_ctr-tst_inits)(r3)
mtctr r1
lwz r1,(init_lr-tst_inits)(r3)
mtlr r1
lwz r1,(init_tar-tst_inits)(r3)
mtspr tar,r1

lwz r0,(init_r0-tst_inits)(r3)
lwz r1,(init_r1-tst_inits)(r3)
lwz r2,(init_r2-tst_inits)(r3)
lwz r4,(init_r4-tst_inits)(r3)
lwz r5,(init_r5-tst_inits)(r3)
lwz r6,(init_r6-tst_inits)(r3)
lwz r7,(init_r7-tst_inits)(r3)
lwz r8,(init_r8-tst_inits)(r3)
lwz r9,(init_r9-tst_inits)(r3)
lwz r10,(init_r10-tst_inits)(r3)
lwz r11,(init_r11-tst_inits)(r3)
lwz r12,(init_r12-tst_inits)(r3)
lwz r13,(init_r13-tst_inits)(r3)
lwz r14,(init_r14-tst_inits)(r3)
lwz r15,(init_r15-tst_inits)(r3)
lwz r16,(init_r16-tst_inits)(r3)
lwz r17,(init_r17-tst_inits)(r3)
lwz r18,(init_r18-tst_inits)(r3)
lwz r19,(init_r19-tst_inits)(r3)
lwz r20,(init_r20-tst_inits)(r3)
lwz r21,(init_r21-tst_inits)(r3)
lwz r22,(init_r22-tst_inits)(r3)
lwz r23,(init_r23-tst_inits)(r3)
lwz r24,(init_r24-tst_inits)(r3)
lwz r25,(init_r25-tst_inits)(r3)
lwz r26,(init_r26-tst_inits)(r3)
lwz r27,(init_r27-tst_inits)(r3)
lwz r28,(init_r28-tst_inits)(r3)
lwz r29,(init_r29-tst_inits)(r3)
lwz r30,(init_r30-tst_inits)(r3)
lwz r31,(init_r31-tst_inits)(r3)
lwz r3,(init_r3-tst_inits)(r3)

b start_tst

# -------------------------------------------------------------------------------------------------
.align 5
start_tst:

# -------------------------------------------------------------------------------------------------
$stream
# -------------------------------------------------------------------------------------------------

b save_results

# -------------------------------------------------------------------------------------------------
.align 5
save_results:
# use a designated spr to save (sprgx, ...)
mtspr SAVESPR,r1
lis r1,tst_results@h
ori r1,r1,tst_results@l
stw r0,(rslt_r0-tst_results)(r1)
stw r2,(rslt_r2-tst_results)(r1)
stw r3,(rslt_r3-tst_results)(r1)
stw r4,(rslt_r4-tst_results)(r1)
stw r5,(rslt_r5-tst_results)(r1)
stw r6,(rslt_r6-tst_results)(r1)
stw r7,(rslt_r7-tst_results)(r1)
stw r8,(rslt_r8-tst_results)(r1)
stw r9,(rslt_r9-tst_results)(r1)
stw r10,(rslt_r10-tst_results)(r1)
stw r11,(rslt_r11-tst_results)(r1)
stw r12,(rslt_r12-tst_results)(r1)
stw r13,(rslt_r13-tst_results)(r1)
stw r14,(rslt_r14-tst_results)(r1)
stw r15,(rslt_r15-tst_results)(r1)
stw r16,(rslt_r16-tst_results)(r1)
stw r17,(rslt_r17-tst_results)(r1)
stw r18,(rslt_r18-tst_results)(r1)
stw r19,(rslt_r19-tst_results)(r1)
stw r20,(rslt_r20-tst_results)(r1)
stw r21,(rslt_r21-tst_results)(r1)
stw r22,(rslt_r22-tst_results)(r1)
stw r23,(rslt_r23-tst_results)(r1)
stw r24,(rslt_r24-tst_results)(r1)
stw r25,(rslt_r25-tst_results)(r1)
stw r26,(rslt_r26-tst_results)(r1)
stw r27,(rslt_r27-tst_results)(r1)
stw r28,(rslt_r28-tst_results)(r1)
stw r29,(rslt_r29-tst_results)(r1)
stw r30,(rslt_r30-tst_results)(r1)
stw r31,(rslt_r31-tst_results)(r1)
mfspr r2,SAVESPR
stw r2,(rslt_r1-tst_results)(r1)
mfcr r2
stw r2,(rslt_cr-tst_results)(r1)
mfxer r2
stw r2,(rslt_xer-tst_results)(r1)
mfctr r2
stw r2,(rslt_ctr-tst_results)(r1)
mflr r2
stw r2,(rslt_lr-tst_results)(r1)
mfspr r2,tar
stw r2,(rslt_tar-tst_results)(r1)

# restore c stuff
lis r3,tst_inits@h
ori r3,r1,tst_inits@l
lwz r1,(save_r1-tst_inits)(r3)
lwz r30,(save_r30-tst_inits)(r3)
lwz r31,(save_r31-tst_inits)(r3)
lis r3,MAGIC@h
ori r3,r3,MAGIC@l

b tst_done

# -------------------------------------------------------------------------------------------------
.align 5
tst_results:

rslt_r0: .long 0xFFFFFFFF
rslt_r1: .long 0xFFFFFFFF
rslt_r2: .long 0xFFFFFFFF
rslt_r3: .long 0xFFFFFFFF
rslt_r4: .long 0xFFFFFFFF
rslt_r5: .long 0xFFFFFFFF
rslt_r6: .long 0xFFFFFFFF
rslt_r7: .long 0xFFFFFFFF
rslt_r8: .long 0xFFFFFFFF
rslt_r9: .long 0xFFFFFFFF
rslt_r10: .long 0xFFFFFFFF
rslt_r11: .long 0xFFFFFFFF
rslt_r12: .long 0xFFFFFFFF
rslt_r13: .long 0xFFFFFFFF
rslt_r14: .long 0xFFFFFFFF
rslt_r15: .long 0xFFFFFFFF
rslt_r16: .long 0xFFFFFFFF
rslt_r17: .long 0xFFFFFFFF
rslt_r18: .long 0xFFFFFFFF
rslt_r19: .long 0xFFFFFFFF
rslt_r20: .long 0xFFFFFFFF
rslt_r21: .long 0xFFFFFFFF
rslt_r22: .long 0xFFFFFFFF
rslt_r23: .long 0xFFFFFFFF
rslt_r24: .long 0xFFFFFFFF
rslt_r25: .long 0xFFFFFFFF
rslt_r26: .long 0xFFFFFFFF
rslt_r27: .long 0xFFFFFFFF
rslt_r28: .long 0xFFFFFFFF
rslt_r29: .long 0xFFFFFFFF
rslt_r30: .long 0xFFFFFFFF
rslt_r31: .long 0xFFFFFFFF

rslt_cr: .long 0xFFFFFFFF
rslt_xer: .long 0xFFFFFFFF
rslt_ctr: .long 0xFFFFFFFF
rslt_lr: .long 0xFFFFFFFF
rslt_tar: .long 0xFFFFFFFF

# -------------------------------------------------------------------------------------------------
.align 5
tst_expects:

expt_r0: .long $expt_r0
expt_r1: .long $expt_r1
expt_r2: .long $expt_r2
expt_r3: .long $expt_r3
expt_r4: .long $expt_r4
expt_r5: .long $expt_r5
expt_r6: .long $expt_r6
expt_r7: .long $expt_r7
expt_r8: .long $expt_r8
expt_r9: .long $expt_r9
expt_r10: .long $expt_r10
expt_r11: .long $expt_r11
expt_r12: .long $expt_r12
expt_r13: .long $expt_r13
expt_r14: .long $expt_r14
expt_r15: .long $expt_r15
expt_r16: .long $expt_r16
expt_r17: .long $expt_r17
expt_r18: .long $expt_r18
expt_r19: .long $expt_r19
expt_r20: .long $expt_r20
expt_r21: .long $expt_r21
expt_r22: .long $expt_r22
expt_r23: .long $expt_r23
expt_r24: .long $expt_r24
expt_r25: .long $expt_r25
expt_r26: .long $expt_r26
expt_r27: .long $expt_r27
expt_r28: .long $expt_r28
expt_r29: .long $expt_r29
expt_r30: .long $expt_r30
expt_r31: .long $expt_r31

expt_cr: .long $expt_cr
expt_xer: .long $expt_xer
expt_ctr: .long $expt_ctr
expt_lr: .long $expt_lr
expt_tar: .long $expt_tar

26
software/arci/simple.tst

@ -1,7 +1,7 @@ @@ -1,7 +1,7 @@

* arci v.0.0001
* -----------------------------------------------------------------------------------------
* Generated: Nov 03 2021 06:00:25 PM GMT
* Generated: Nov 07 2021 01:44:35 AM GMT
*

* Initialization
@ -9,10 +9,9 @@ @@ -9,10 +9,9 @@
R CIA 00120000
R CR 00000000 * F0:0 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R XER 00000000
R SRR0 00000000
R SRR1 00000000
R DAR 00000000
R DSISR 00000000
R CTR F0000000
R LR 00000000
R TAR 00000000
R R00 00000000 * 0
R R01 00000000 * 0
R R02 00000000 * 0
@ -48,23 +47,23 @@ R R31 00000000 * 0 @@ -48,23 +47,23 @@ R R31 00000000 * 0

* Instructions

I 00120000 addi R03,R03,1
I 00120000 addi r3,r3,1
R R03 00000001 * 1
R CIA 00120004

I 00120004 addi R03,R03,1
I 00120004 addi r3,r3,1
R R03 00000002 * 2
R CIA 00120008

I 00120008 addi R03,R03,1
I 00120008 addi r3,r3,1
R R03 00000003 * 3
R CIA 0012000C

I 0012000C addi R04,R00,-3
I 0012000C addi r4,r0,-3
R R04 FFFFFFFD * 4294967293
R CIA 00120010

I 00120010 add. R04,R04,R03
I 00120010 add. r4,r4,r3
R R04 00000000 * 0
R CR 20000000 * F0:2 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R CIA 00120014
@ -82,10 +81,9 @@ R R04 00000000 * 0 @@ -82,10 +81,9 @@ R R04 00000000 * 0
R CIA 00120014
R CR 20000000 * F0:2 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0
R XER 00000000
R SRR0 00000000
R SRR1 00000000
R DAR 00000000
R DSISR 00000000
R CTR F0000000
R LR 00000000
R TAR 00000000
R R00 00000000 * 0
R R01 00000000 * 0
R R02 00000000 * 0

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