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mithro test

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master
wtf 2 years ago
parent 749bd98c9b
commit 8b01139c2d
3 changed files with 125 additions and 1 deletions
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45
build/litex/litex-1099/mithro/csr.csv
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@ -0,0 +1,45 @@
#--------------------------------------------------------------------------------
# Auto-generated by Migen (7507a2b) & LiteX (feca1c47) on 2021-11-11 13:01:55
#--------------------------------------------------------------------------------
csr_base,ctrl,0xfff00800,,
csr_base,identifier_mem,0xfff01000,,
csr_base,timer0,0xfff01800,,
csr_base,uart,0xfff02000,,
csr_register,ctrl_reset,0xfff00800,1,rw
csr_register,ctrl_scratch,0xfff00804,1,rw
csr_register,ctrl_bus_errors,0xfff00808,1,ro
csr_register,timer0_load,0xfff01800,1,rw
csr_register,timer0_reload,0xfff01804,1,rw
csr_register,timer0_en,0xfff01808,1,rw
csr_register,timer0_update_value,0xfff0180c,1,rw
csr_register,timer0_value,0xfff01810,1,ro
csr_register,timer0_ev_status,0xfff01814,1,ro
csr_register,timer0_ev_pending,0xfff01818,1,rw
csr_register,timer0_ev_enable,0xfff0181c,1,rw
csr_register,uart_rxtx,0xfff02000,1,rw
csr_register,uart_txfull,0xfff02004,1,ro
csr_register,uart_rxempty,0xfff02008,1,ro
csr_register,uart_ev_status,0xfff0200c,1,ro
csr_register,uart_ev_pending,0xfff02010,1,rw
csr_register,uart_ev_enable,0xfff02014,1,rw
csr_register,uart_txempty,0xfff02018,1,ro
csr_register,uart_rxfull,0xfff0201c,1,ro
constant,config_clock_frequency,100000000,,
constant,config_cpu_has_interrupt,None,,
constant,config_cpu_reset_addr,0,,
constant,config_cpu_type_a2p,None,,
constant,config_cpu_variant_standard,None,,
constant,config_cpu_human_name,a2p_wb,,
constant,config_cpu_nop,nop,,
constant,config_with_build_time,None,,
constant,uart_polling,None,,
constant,config_csr_data_width,32,,
constant,config_csr_alignment,32,,
constant,config_bus_standard,wishbone,,
constant,config_bus_data_width,32,,
constant,config_bus_address_width,32,,
constant,timer0_interrupt,1,,
constant,uart_interrupt,0,,
memory_region,rom,0x00000000,65536,cached
memory_region,sram,0x00100000,524288,cached
memory_region,csr,0xfff00000,65536,io
1 #--------------------------------------------------------------------------------
2 # Auto-generated by Migen (7507a2b) & LiteX (feca1c47) on 2021-11-11 13:01:55
3 #--------------------------------------------------------------------------------
4 csr_base,ctrl,0xfff00800,,
5 csr_base,identifier_mem,0xfff01000,,
6 csr_base,timer0,0xfff01800,,
7 csr_base,uart,0xfff02000,,
8 csr_register,ctrl_reset,0xfff00800,1,rw
9 csr_register,ctrl_scratch,0xfff00804,1,rw
10 csr_register,ctrl_bus_errors,0xfff00808,1,ro
11 csr_register,timer0_load,0xfff01800,1,rw
12 csr_register,timer0_reload,0xfff01804,1,rw
13 csr_register,timer0_en,0xfff01808,1,rw
14 csr_register,timer0_update_value,0xfff0180c,1,rw
15 csr_register,timer0_value,0xfff01810,1,ro
16 csr_register,timer0_ev_status,0xfff01814,1,ro
17 csr_register,timer0_ev_pending,0xfff01818,1,rw
18 csr_register,timer0_ev_enable,0xfff0181c,1,rw
19 csr_register,uart_rxtx,0xfff02000,1,rw
20 csr_register,uart_txfull,0xfff02004,1,ro
21 csr_register,uart_rxempty,0xfff02008,1,ro
22 csr_register,uart_ev_status,0xfff0200c,1,ro
23 csr_register,uart_ev_pending,0xfff02010,1,rw
24 csr_register,uart_ev_enable,0xfff02014,1,rw
25 csr_register,uart_txempty,0xfff02018,1,ro
26 csr_register,uart_rxfull,0xfff0201c,1,ro
27 constant,config_clock_frequency,100000000,,
28 constant,config_cpu_has_interrupt,None,,
29 constant,config_cpu_reset_addr,0,,
30 constant,config_cpu_type_a2p,None,,
31 constant,config_cpu_variant_standard,None,,
32 constant,config_cpu_human_name,a2p_wb,,
33 constant,config_cpu_nop,nop,,
34 constant,config_with_build_time,None,,
35 constant,uart_polling,None,,
36 constant,config_csr_data_width,32,,
37 constant,config_csr_alignment,32,,
38 constant,config_bus_standard,wishbone,,
39 constant,config_bus_data_width,32,,
40 constant,config_bus_address_width,32,,
41 constant,timer0_interrupt,1,,
42 constant,uart_interrupt,0,,
43 memory_region,rom,0x00000000,65536,cached
44 memory_region,sram,0x00100000,524288,cached
45 memory_region,csr,0xfff00000,65536,io

3
build/litex/litex-1099/simple/tim.py → build/litex/litex-1099/mithro/mithro.py
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@ -40,6 +40,7 @@ from litex.soc.interconnect import wishbone


from litex.soc.cores import uart from litex.soc.cores import uart
from litex.soc.cores.uart import UART from litex.soc.cores.uart import UART
from litex.soc.cores.uart import RS232PHY
from litex.soc.cores.uart import UARTPHY from litex.soc.cores.uart import UARTPHY
from litex.soc.cores.uart import UARTBone from litex.soc.cores.uart import UARTBone
from litex.soc.cores.uart import UARTWishboneBridge from litex.soc.cores.uart import UARTWishboneBridge
@ -130,7 +131,7 @@ def main():


soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_analyzer = args.with_analyzer, #with_analyzer = args.with_analyzer,
**soc_sdram_argdict(args) **soc_sdram_argdict(args)
) )


78
build/litex/litex-1099/mithro/mithro.txt
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@ -0,0 +1,78 @@
Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :)
Namespace(build=False, bus_address_width=32, bus_data_width=32, bus_standard='wishbone', bus_timeout=1000000.0, cpu_cfu=None, cpu_reset_address=None, cpu_type=None, cpu_variant=None, csr_address_width=14, csr_csv='csr.csv', csr_data_width=None, csr_json=None, csr_ordering='big', csr_paging=2048, csr_svd=None, doc=False, gateware_dir=None, generated_dir=None, ident=None, ident_version=None, include_dir=None, integrated_main_ram_size=None, integrated_rom_init=None, integrated_rom_size=131072, integrated_sram_size=8192, l2_size=8192, load=False, memory_x=None, no_compile_gateware=False, no_compile_software=True, no_ctrl=False, no_timer=False, no_uart=False, output_dir=None, software_dir=None, sys_clk_freq=100000000.0, timer_uptime=False, uart_baudrate=None, uart_fifo_depth=16, uart_name='serial')
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-11-11 13:48:04)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a35t-CPG236-1.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
INFO:SoC:CPU overriding sram mapping from 0x1000000 to 0x4000.
INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:S7MMCM:Creating S7MMCM, speedgrade -1.
INFO:S7MMCM:Registering Single Ended ClkIn of 12.00MHz.
INFO:S7MMCM:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S7MMCM:Creating ClkOut1 sys2x of 200.00MHz (+-10000.00ppm).
INFO:S7MMCM:Creating ClkOut2 idelay of 200.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:uart_1_phy CSR allocated at Location 0.
INFO:SoCCSRHandler:uart_1 CSR allocated at Location 1.
INFO:S7MMCM:Config:
divclk_divide : 1
clkout0_freq : 100.00MHz
clkout0_divide: 6
clkout0_phase : 0.00°
clkout1_freq : 200.00MHz
clkout1_divide: 3
clkout1_phase : 0.00°
clkout2_freq : 200.00MHz
clkout2_divide: 3
clkout2_phase : 0.00°
vco : 600.00MHz
clkfbout_mult : 50
INFO:SoCBusHandler:csr Region added at Origin: 0xfff00000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 1).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 2.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 3.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 4.
INFO:SoCCSRHandler:uart CSR allocated at Location 5.
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
ERROR:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (1)
csr : Origin: 0xfff00000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (1)
- csr
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