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34 lines
848 B
Markdown
34 lines
848 B
Markdown
# Using Litex to build a Caravel User Project Area
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Create a module usable for FPGA and tech mapping, containing various Litex structures like CSR, WB, UART, I2C, etc. and
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custom verilog modules (core, async RAM, GPIO, etc.).
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* create a virtual platform corresponding to the I/O on the Caravel User module
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* create virtual 'soc' design using that platform
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* module can be used for OL synthesis (expand_type set for tech)
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* module can be included in FPGA SOC for testing and development (expand_type set for inferred)
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* create real soc incorporating above, plus clocks, real GPIO connections, etc.
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### Virtual Platform
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* create user area
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```
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a2p_site.py
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cp build/caravel_user/gateware/mem.init .
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cp build/caravel_user/gateware/caravel_user.v .
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```
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* OL didn't die
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```
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make DESIGN_CONFIG=./designs/sky130hd/a2p_litex/config.mk
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```
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