An experimental small core based on VexRiscv, written in Scala
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#ifndef __IRQ_H |
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#define __IRQ_H |
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static inline void irq_setmask(unsigned int mask) { |
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} |
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static inline unsigned int irq_getmask(void) { |
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return 0; |
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} |
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static inline unsigned int irq_pending(void) { |
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return 0; |
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} |
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static inline void irq_setie(unsigned int mask) { |
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} |
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#endif |
