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4a8aeab3be
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3 years ago | |
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| a2wb.v | 3 years ago | |
| readme.md | 3 years ago | |
readme.md
A2 Interfaces to WB
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core interfaces
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A2I/A2O A2L2 bus
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Single (combined I/D) w/SMP extensions
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Dual (separate I/D) WB buses w/SMP extensions
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bus interface
- WB (non-SMP)
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functions
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arbitrates for WB bus
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queues one or more core commands
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point of coherncy for larx/stcx, sync, tlbie, etc. for multicores below it (single/mulithread)
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address compares necessary for ordering/coherency
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optional mailbox interface for core-core peer and broadcast
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Possible configurations
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one core, WB: pass-through with SMP functions
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one core, A2L2: bridge with SMP functions
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multi-core: bridge for A2L2, queueing, arbitration, and SMP functions