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23 lines
437 B
VHDL
23 lines
437 B
VHDL
4 years ago
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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entity random is
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port (
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clk : in std_ulogic;
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data : out std_ulogic_vector(63 downto 0);
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raw : out std_ulogic_vector(63 downto 0);
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err : out std_ulogic
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);
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end entity random;
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architecture behaviour of random is
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begin
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data <= (others => '1');
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raw <= (others => '1');
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err <= '1';
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end behaviour;
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