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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.decode_types.all;
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use work.crhelpers.all;
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entity divider is
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port (
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clk : in std_logic;
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rst : in std_logic;
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d_in : in Decode2ToDividerType;
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d_out : out DividerToWritebackType
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);
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end entity divider;
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architecture behaviour of divider is
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signal dend : std_ulogic_vector(127 downto 0);
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signal div : unsigned(63 downto 0);
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signal quot : std_ulogic_vector(63 downto 0);
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signal result : std_ulogic_vector(63 downto 0);
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signal sresult : std_ulogic_vector(63 downto 0);
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signal qbit : std_ulogic;
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signal running : std_ulogic;
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signal signcheck : std_ulogic;
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signal count : unsigned(6 downto 0);
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signal neg_result : std_ulogic;
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signal is_modulus : std_ulogic;
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signal is_32bit : std_ulogic;
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signal extended : std_ulogic;
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signal rc : std_ulogic;
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signal write_reg : std_ulogic_vector(4 downto 0);
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function compare_zero(value : std_ulogic_vector(63 downto 0); is_32 : std_ulogic)
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return std_ulogic_vector is
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begin
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if is_32 = '1' then
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if value(31) = '1' then
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return "1000";
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elsif unsigned(value(30 downto 0)) > 0 then
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return "0100";
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else
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return "0010";
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end if;
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else
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if value(63) = '1' then
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return "1000";
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elsif unsigned(value(62 downto 0)) > 0 then
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return "0100";
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else
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return "0010";
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end if;
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end if;
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end function compare_zero;
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begin
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divider_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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dend <= (others => '0');
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div <= (others => '0');
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quot <= (others => '0');
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running <= '0';
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count <= "0000000";
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elsif d_in.valid = '1' then
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if d_in.is_extended = '1' and not (d_in.is_signed = '1' and d_in.dividend(63) = '1') then
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dend <= d_in.dividend & x"0000000000000000";
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else
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dend <= x"0000000000000000" & d_in.dividend;
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end if;
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div <= unsigned(d_in.divisor);
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quot <= (others => '0');
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write_reg <= d_in.write_reg;
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neg_result <= '0';
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is_modulus <= d_in.is_modulus;
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extended <= d_in.is_extended;
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is_32bit <= d_in.is_32bit;
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rc <= d_in.rc;
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count <= "0000000";
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running <= '1';
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signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
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elsif signcheck = '1' then
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signcheck <= '0';
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neg_result <= dend(63) xor (div(63) and not is_modulus);
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if dend(63) = '1' then
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if extended = '1' then
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dend <= std_ulogic_vector(- signed(dend(63 downto 0))) & x"0000000000000000";
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else
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dend <= x"0000000000000000" & std_ulogic_vector(- signed(dend(63 downto 0)));
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end if;
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end if;
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if div(63) = '1' then
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div <= unsigned(- signed(div));
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end if;
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elsif running = '1' then
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if count = "0111111" then
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running <= '0';
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end if;
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if dend(127) = '1' or unsigned(dend(126 downto 63)) >= div then
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dend <= std_ulogic_vector(unsigned(dend(126 downto 63)) - div) &
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dend(62 downto 0) & '0';
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quot <= quot(62 downto 0) & '1';
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count <= count + 1;
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elsif dend(127 downto 56) = x"000000000000000000" and count(5 downto 3) /= "111" then
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-- consume 8 bits of zeroes in one cycle
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dend <= dend(119 downto 0) & x"00";
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quot <= quot(55 downto 0) & x"00";
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count <= count + 8;
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else
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dend <= dend(126 downto 0) & '0';
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quot <= quot(62 downto 0) & '0';
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count <= count + 1;
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end if;
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else
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count <= "0000000";
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end if;
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end if;
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end process;
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divider_1: process(all)
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begin
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d_out <= DividerToWritebackInit;
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d_out.write_reg_nr <= write_reg;
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if is_modulus = '1' then
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result <= dend(127 downto 64);
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else
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result <= quot;
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end if;
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if neg_result = '1' then
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sresult <= std_ulogic_vector(- signed(result));
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else
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sresult <= result;
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end if;
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d_out.write_reg_data <= sresult;
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if count(6) = '1' then
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d_out.valid <= '1';
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d_out.write_reg_enable <= '1';
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if rc = '1' then
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d_out.write_cr_enable <= '1';
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d_out.write_cr_mask <= num_to_fxm(0);
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d_out.write_cr_data <= compare_zero(sresult, is_32bit) & x"0000000";
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end if;
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end if;
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end process;
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end architecture behaviour;
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