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#define _POSIX_C_SOURCE 200809L
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#define _GNU_SOURCE
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <getopt.h>
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#include <poll.h>
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#include <signal.h>
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#include <fcntl.h>
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#include <netdb.h>
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#include <ctype.h>
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#include <sys/types.h>
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#include <sys/socket.h>
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#include <netinet/in.h>
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#include <urjtag/urjtag.h>
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#include <inttypes.h>
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#define DBG_WB_ADDR 0x00
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#define DBG_WB_DATA 0x01
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#define DBG_WB_CTRL 0x02
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#define DBG_CORE_CTRL 0x10
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#define DBG_CORE_CTRL_STOP (1 << 0)
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#define DBG_CORE_CTRL_RESET (1 << 1)
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#define DBG_CORE_CTRL_ICRESET (1 << 2)
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#define DBG_CORE_CTRL_STEP (1 << 3)
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#define DBG_CORE_CTRL_START (1 << 4)
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#define DBG_CORE_STAT 0x11
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#define DBG_CORE_STAT_STOPPING (1 << 0)
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#define DBG_CORE_STAT_STOPPED (1 << 1)
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#define DBG_CORE_STAT_TERM (1 << 2)
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#define DBG_CORE_NIA 0x12
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#define DBG_CORE_MSR 0x13
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#define DBG_CORE_GSPR_INDEX 0x14
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#define DBG_CORE_GSPR_DATA 0x15
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static bool debug;
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struct backend {
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int (*init)(const char *target);
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int (*reset)(void);
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int (*command)(uint8_t op, uint8_t addr, uint64_t *data);
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};
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static struct backend *b;
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static void check(int r, const char *failstr)
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{
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if (r >= 0)
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return;
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fprintf(stderr, "Error %s\n", failstr);
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exit(1);
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}
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/* -------------- SIM backend -------------- */
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static int sim_fd = -1;
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static int sim_init(const char *target)
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{
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struct sockaddr_in saddr;
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struct hostent *hp;
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const char *p, *host;
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int port, rc;
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if (!target)
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target = "localhost:13245";
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p = strchr(target, ':');
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host = strndup(target, p - target);
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if (p && *p)
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p++;
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else
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p = "13245";
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port = strtoul(p, NULL, 10);
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if (debug)
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printf("Opening sim backend host '%s' port %d\n", host, port);
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sim_fd = socket(PF_INET, SOCK_STREAM, 0);
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if (sim_fd < 0) {
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fprintf(stderr, "Error opening socket: %s\n",
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strerror(errno));
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return -1;
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}
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hp = gethostbyname(host);
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if (!hp) {
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fprintf(stderr,"Unknown host '%s'\n", host);
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return -1;
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}
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memcpy(&saddr.sin_addr, hp->h_addr, hp->h_length);
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saddr.sin_port = htons(port);
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saddr.sin_family = PF_INET;
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rc = connect(sim_fd, (struct sockaddr *)&saddr, sizeof(saddr));
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if (rc < 0) {
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close(sim_fd);
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fprintf(stderr,"Connection to '%s' failed: %s\n",
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host, strerror(errno));
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return -1;
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}
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return 0;
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}
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static int sim_reset(void)
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{
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return 0;
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}
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static void add_bits(uint8_t **p, int *b, uint64_t d, int c)
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{
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uint8_t md = 1 << *b;
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uint64_t ms = 1;
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while (c--) {
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if (d & ms)
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(**p) |= md;
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ms <<= 1;
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if (*b == 7) {
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*b = 0;
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(*p)++;
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md = 1;
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} else {
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(*b)++;
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md <<= 1;
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}
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}
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}
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static uint64_t read_bits(uint8_t **p, int *b, int c)
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{
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uint8_t ms = 1 << *b;
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uint64_t md = 1;
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uint64_t d = 0;
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while (c--) {
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if ((**p) & ms)
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d |= md;
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md <<= 1;
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if (*b == 7) {
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*b = 0;
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(*p)++;
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ms = 1;
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} else {
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(*b)++;
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ms <<= 1;
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}
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}
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return d;
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}
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static int sim_command(uint8_t op, uint8_t addr, uint64_t *data)
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{
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uint8_t buf[16], *p;
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uint64_t d = data ? *data : 0;
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int r, b = 0;
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memset(buf, 0, 16);
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p = buf+1;
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add_bits(&p, &b, op, 2);
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add_bits(&p, &b, d, 64);
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add_bits(&p, &b, addr, 8);
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if (b)
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p++;
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buf[0] = 74;
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if (0)
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{
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int i;
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for (i=0; i<(p-buf); i++)
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printf("%02x ", buf[i]);
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printf("\n");
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}
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write(sim_fd, buf, p - buf);
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r = read(sim_fd, buf, 127);
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if (0 && r > 0) {
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int i;
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for (i=0; i<r; i++)
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printf("%02x ", buf[i]);
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printf("\n");
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}
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p = buf+1;
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b = 0;
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r = read_bits(&p, &b, 2);
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if (data)
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*data = read_bits(&p, &b, 64);
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return r;
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}
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static struct backend sim_backend = {
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.init = sim_init,
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.reset = sim_reset,
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.command = sim_command,
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};
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/* -------------- JTAG backend -------------- */
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static urj_chain_t *jc;
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static int jtag_init(const char *target)
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{
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const char *sep;
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const char *cable;
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char *params[] = { NULL, };
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urj_part_t *p;
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uint32_t id;
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int rc, part;
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if (!target)
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target = "DigilentHS1";
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sep = strchr(target, ':');
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cable = strndup(target, sep - target);
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if (sep && *sep) {
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fprintf(stderr, "jtag cable params not supported yet\n");
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return -1;
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}
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if (debug)
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printf("Opening jtag backend cable '%s'\n", cable);
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jc = urj_tap_chain_alloc();
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if (!jc) {
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fprintf(stderr, "Failed to alloc JTAG\n");
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return -1;
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}
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jc->main_part = 0;
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rc = urj_tap_chain_connect(jc, cable, params);
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if (rc != URJ_STATUS_OK) {
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fprintf(stderr, "JTAG cable detect failed\n");
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return -1;
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}
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/* XXX Hard wire part 0, that might need to change (use params and detect !) */
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rc = urj_tap_manual_add(jc, 6);
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if (rc < 0) {
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fprintf(stderr, "JTAG failed to add part !\n");
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return -1;
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}
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if (jc->parts == NULL || jc->parts->len == 0) {
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fprintf(stderr, "JTAG Something's wrong after adding part !\n");
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return -1;
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}
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urj_part_parts_set_instruction(jc->parts, "BYPASS");
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jc->active_part = part = 0;
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p = urj_tap_chain_active_part(jc);
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if (!p) {
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fprintf(stderr, "Failed to get active JTAG part\n");
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return -1;
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}
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rc = urj_part_data_register_define(p, "IDCODE_REG", 32);
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if (rc != URJ_STATUS_OK) {
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fprintf(stderr, "JTAG failed to add IDCODE_REG register !\n");
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return -1;
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}
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if (urj_part_instruction_define(p, "IDCODE", "001001", "IDCODE_REG") == NULL) {
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fprintf(stderr, "JTAG failed to add IDCODE instruction !\n");
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return -1;
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}
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rc = urj_part_data_register_define(p, "USER2_REG", 74);
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if (rc != URJ_STATUS_OK) {
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fprintf(stderr, "JTAG failed to add USER2_REG register !\n");
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return -1;
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}
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if (urj_part_instruction_define(p, "USER2", "000011", "USER2_REG") == NULL) {
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fprintf(stderr, "JTAG failed to add USER2 instruction !\n");
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return -1;
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}
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urj_part_set_instruction(p, "IDCODE");
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urj_tap_chain_shift_instructions(jc);
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urj_tap_chain_shift_data_registers(jc, 1);
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id = urj_tap_register_get_value(p->active_instruction->data_register->out);
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printf("Found device ID: 0x%08x\n", id);
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urj_part_set_instruction(p, "USER2");
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urj_tap_chain_shift_instructions(jc);
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return 0;
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}
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static int jtag_reset(void)
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{
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return 0;
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}
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static int jtag_command(uint8_t op, uint8_t addr, uint64_t *data)
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{
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urj_part_t *p = urj_tap_chain_active_part(jc);
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urj_part_instruction_t *insn;
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urj_data_register_t *dr;
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uint64_t d = data ? *data : 0;
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int rc;
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if (!p)
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return -1;
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insn = p->active_instruction;
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if (!insn)
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return -1;
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dr = insn->data_register;
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if (!dr)
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return -1;
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rc = urj_tap_register_set_value_bit_range(dr->in, op, 1, 0);
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if (rc != URJ_STATUS_OK)
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return -1;
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rc = urj_tap_register_set_value_bit_range(dr->in, d, 65, 2);
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if (rc != URJ_STATUS_OK)
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return -1;
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rc = urj_tap_register_set_value_bit_range(dr->in, addr, 73, 66);
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if (rc != URJ_STATUS_OK)
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return -1;
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rc = urj_tap_chain_shift_data_registers(jc, 1);
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if (rc != URJ_STATUS_OK)
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return -1;
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rc = urj_tap_register_get_value_bit_range(dr->out, 1, 0);
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if (data)
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*data = urj_tap_register_get_value_bit_range(dr->out, 65, 2);
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return rc;
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}
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static struct backend jtag_backend = {
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.init = jtag_init,
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.reset = jtag_reset,
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.command = jtag_command,
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};
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static int dmi_read(uint8_t addr, uint64_t *data)
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{
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int rc;
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rc = b->command(1, addr, data);
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if (rc < 0)
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return rc;
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for (;;) {
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rc = b->command(0, 0, data);
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if (rc < 0)
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return rc;
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if (rc == 0)
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return 0;
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if (rc != 3)
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fprintf(stderr, "Unknown status code %d !\n", rc);
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}
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}
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static int dmi_write(uint8_t addr, uint64_t data)
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{
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int rc;
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rc = b->command(2, addr, &data);
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if (rc < 0)
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return rc;
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for (;;) {
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rc = b->command(0, 0, NULL);
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if (rc < 0)
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return rc;
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if (rc == 0)
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return 0;
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if (rc != 3)
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fprintf(stderr, "Unknown status code %d !\n", rc);
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}
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}
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static void core_status(void)
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{
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uint64_t stat, nia, msr;
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const char *statstr, *statstr2;
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check(dmi_read(DBG_CORE_STAT, &stat), "reading core status");
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check(dmi_read(DBG_CORE_NIA, &nia), "reading core NIA");
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check(dmi_read(DBG_CORE_MSR, &msr), "reading core MSR");
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if (debug)
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printf("Core status = 0x%llx\n", (unsigned long long)stat);
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statstr = "running";
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statstr2 = "";
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if (stat & DBG_CORE_STAT_STOPPED) {
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statstr = "stopped";
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if (!(stat & DBG_CORE_STAT_STOPPING))
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|
|
statstr2 = " (restarting?)";
|
|
|
|
else if (stat & DBG_CORE_STAT_TERM)
|
|
|
|
statstr2 = " (terminated)";
|
|
|
|
} else if (stat & DBG_CORE_STAT_STOPPING)
|
|
|
|
statstr = "stopping";
|
|
|
|
else if (stat & DBG_CORE_STAT_TERM)
|
|
|
|
statstr = "odd state (TERM but no STOP)";
|
|
|
|
printf("Core: %s%s\n", statstr, statstr2);
|
|
|
|
printf(" NIA: %016" PRIx64 "\n", nia);
|
|
|
|
printf(" MSR: %016" PRIx64 "\n", msr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void core_stop(void)
|
|
|
|
{
|
|
|
|
check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_STOP), "stopping core");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void core_start(void)
|
|
|
|
{
|
|
|
|
check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_START), "starting core");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void core_reset(void)
|
|
|
|
{
|
|
|
|
check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_RESET), "resetting core");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void core_step(void)
|
|
|
|
{
|
|
|
|
uint64_t stat;
|
|
|
|
|
|
|
|
check(dmi_read(DBG_CORE_STAT, &stat), "reading core status");
|
|
|
|
|
|
|
|
if (!(stat & DBG_CORE_STAT_STOPPED)) {
|
|
|
|
printf("Core not stopped !\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_STEP), "stepping core");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void icache_reset(void)
|
|
|
|
{
|
|
|
|
check(dmi_write(DBG_CORE_CTRL, DBG_CORE_CTRL_ICRESET), "resetting icache");
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *fast_spr_names[] =
|
|
|
|
{
|
|
|
|
"lr", "ctr", "srr0", "srr1", "hsrr0", "hsrr1",
|
|
|
|
"sprg0", "sprg1", "sprg2", "sprg3",
|
|
|
|
"hsprg0", "hsprg1", "xer"
|
|
|
|
};
|
|
|
|
|
|
|
|
static void gpr_read(uint64_t reg, uint64_t count)
|
|
|
|
{
|
|
|
|
uint64_t data;
|
|
|
|
|
|
|
|
reg &= 0x3f;
|
|
|
|
if (reg + count > 64)
|
|
|
|
count = 64 - reg;
|
|
|
|
for (; count != 0; --count, ++reg) {
|
|
|
|
check(dmi_write(DBG_CORE_GSPR_INDEX, reg), "setting GPR index");
|
|
|
|
data = 0xdeadbeef;
|
|
|
|
check(dmi_read(DBG_CORE_GSPR_DATA, &data), "reading GPR data");
|
|
|
|
if (reg <= 31)
|
|
|
|
printf("r%"PRId64, reg);
|
|
|
|
else if ((reg - 32) < sizeof(fast_spr_names) / sizeof(fast_spr_names[0]))
|
|
|
|
printf("%s", fast_spr_names[reg - 32]);
|
|
|
|
else
|
|
|
|
printf("gspr%"PRId64, reg);
|
|
|
|
printf(":\t%016"PRIx64"\n", data);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mem_read(uint64_t addr, uint64_t count)
|
|
|
|
{
|
|
|
|
uint64_t data;
|
|
|
|
int i, rc;
|
|
|
|
|
|
|
|
rc = dmi_write(DBG_WB_CTRL, 0x7ff);
|
|
|
|
if (rc < 0)
|
|
|
|
return;
|
|
|
|
rc = dmi_write(DBG_WB_ADDR, addr);
|
|
|
|
if (rc < 0)
|
|
|
|
return;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
rc = dmi_read(DBG_WB_DATA, &data);
|
|
|
|
if (rc < 0)
|
|
|
|
return;
|
|
|
|
printf("%016llx: %016llx\n",
|
|
|
|
(unsigned long long)addr,
|
|
|
|
(unsigned long long)data);
|
|
|
|
addr += 8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mem_write(uint64_t addr, uint64_t data)
|
|
|
|
{
|
|
|
|
check(dmi_write(DBG_WB_CTRL, 0x7ff), "writing WB_CTRL");
|
|
|
|
check(dmi_write(DBG_WB_ADDR, addr), "writing WB_ADDR");
|
|
|
|
check(dmi_write(DBG_WB_DATA, data), "writing WB_DATA");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void load(const char *filename, uint64_t addr)
|
|
|
|
{
|
|
|
|
uint64_t data;
|
|
|
|
int fd, rc, count;
|
|
|
|
|
|
|
|
fd = open(filename, O_RDONLY);
|
|
|
|
if (fd < 0) {
|
|
|
|
fprintf(stderr, "Failed to open '%s': %s\n", filename, strerror(errno));
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
check(dmi_write(DBG_WB_CTRL, 0x7ff), "writing WB_CTRL");
|
|
|
|
check(dmi_write(DBG_WB_ADDR, addr), "writing WB_ADDR");
|
|
|
|
count = 0;
|
|
|
|
for (;;) {
|
|
|
|
data = 0;
|
|
|
|
rc = read(fd, &data, 8);
|
|
|
|
if (rc <= 0)
|
|
|
|
break;
|
|
|
|
// if (rc < 8) XXX fixup endian ?
|
|
|
|
check(dmi_write(DBG_WB_DATA, data), "writing WB_DATA");
|
|
|
|
count += 8;
|
|
|
|
if (!(count % 1024))
|
|
|
|
printf("%x...\n", count);
|
|
|
|
}
|
|
|
|
printf("%x done.\n", count);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void usage(const char *cmd)
|
|
|
|
{
|
|
|
|
fprintf(stderr, "Usage: %s -b <jtag|sim> <command> <args>\n", cmd);
|
|
|
|
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, " CPU core:\n");
|
|
|
|
fprintf(stderr, " start\n");
|
|
|
|
fprintf(stderr, " stop\n");
|
|
|
|
fprintf(stderr, " step\n");
|
|
|
|
fprintf(stderr, " creset core reset\n");
|
|
|
|
fprintf(stderr, " icreset icache reset\n");
|
|
|
|
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, " Memory:\n");
|
|
|
|
fprintf(stderr, " mr <hex addr>\n");
|
|
|
|
fprintf(stderr, " mw <hex addr> <hex value>\n");
|
|
|
|
fprintf(stderr, " load <file> [addr] If omitted address is 0\n");
|
|
|
|
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, " Registers:\n");
|
|
|
|
fprintf(stderr, " gpr <reg> [count]\n");
|
|
|
|
fprintf(stderr, " status\n");
|
|
|
|
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, " JTAG:\n");
|
|
|
|
fprintf(stderr, " dmiread <hex addr>\n");
|
|
|
|
fprintf(stderr, " dmiwrite <hex addr> <hex value>\n");
|
|
|
|
fprintf(stderr, " quit\n");
|
|
|
|
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
int main(int argc, char *argv[])
|
|
|
|
{
|
|
|
|
const char *progname = argv[0];
|
|
|
|
const char *target = NULL;
|
|
|
|
int rc, i = 1;
|
|
|
|
|
|
|
|
b = NULL;
|
|
|
|
|
|
|
|
while(1) {
|
|
|
|
int c, oindex;
|
|
|
|
static struct option lopts[] = {
|
|
|
|
{ "help", no_argument, 0, 'h' },
|
|
|
|
{ "backend", required_argument, 0, 'b' },
|
|
|
|
{ "target", required_argument, 0, 't' },
|
|
|
|
{ "debug", no_argument, 0, 'd' },
|
|
|
|
{ 0, 0, 0, 0 }
|
|
|
|
};
|
|
|
|
c = getopt_long(argc, argv, "dhb:t:", lopts, &oindex);
|
|
|
|
if (c < 0)
|
|
|
|
break;
|
|
|
|
switch(c) {
|
|
|
|
case 'h':
|
|
|
|
usage(progname);
|
|
|
|
break;
|
|
|
|
case 'b':
|
|
|
|
if (strcmp(optarg, "sim") == 0)
|
|
|
|
b = &sim_backend;
|
|
|
|
else if (strcmp(optarg, "jtag") == 0)
|
|
|
|
b = &jtag_backend;
|
|
|
|
else {
|
|
|
|
fprintf(stderr, "Unknown backend %s\n", optarg);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 't':
|
|
|
|
target = optarg;
|
|
|
|
break;
|
|
|
|
case 'd':
|
|
|
|
debug = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (b == NULL) {
|
|
|
|
fprintf(stderr, "No backend selected\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = b->init(target);
|
|
|
|
if (rc < 0)
|
|
|
|
exit(1);
|
|
|
|
for (i = optind; i < argc; i++) {
|
|
|
|
if (strcmp(argv[i], "dmiread") == 0) {
|
|
|
|
uint8_t addr;
|
|
|
|
uint64_t data;
|
|
|
|
|
|
|
|
if ((i+1) >= argc)
|
|
|
|
usage(argv[0]);
|
|
|
|
addr = strtoul(argv[++i], NULL, 16);
|
|
|
|
dmi_read(addr, &data);
|
|
|
|
printf("%02x: %016llx\n", addr, (unsigned long long)data);
|
|
|
|
} else if (strcmp(argv[i], "dmiwrite") == 0) {
|
|
|
|
uint8_t addr;
|
|
|
|
uint64_t data;
|
|
|
|
|
|
|
|
if ((i+2) >= argc)
|
|
|
|
usage(argv[0]);
|
|
|
|
addr = strtoul(argv[++i], NULL, 16);
|
|
|
|
data = strtoul(argv[++i], NULL, 16);
|
|
|
|
dmi_write(addr, data);
|
|
|
|
} else if (strcmp(argv[i], "creset") == 0) {
|
|
|
|
core_reset();
|
|
|
|
} else if (strcmp(argv[i], "icreset") == 0) {
|
|
|
|
icache_reset();
|
|
|
|
} else if (strcmp(argv[i], "stop") == 0) {
|
|
|
|
core_stop();
|
|
|
|
} else if (strcmp(argv[i], "start") == 0) {
|
|
|
|
core_start();
|
|
|
|
} else if (strcmp(argv[i], "step") == 0) {
|
|
|
|
core_step();
|
|
|
|
} else if (strcmp(argv[i], "quit") == 0) {
|
|
|
|
dmi_write(0xff, 0);
|
|
|
|
} else if (strcmp(argv[i], "status") == 0) {
|
|
|
|
/* do nothing, always done below */
|
|
|
|
} else if (strcmp(argv[i], "mr") == 0) {
|
|
|
|
uint64_t addr, count = 1;
|
|
|
|
|
|
|
|
if ((i+1) >= argc)
|
|
|
|
usage(argv[0]);
|
|
|
|
addr = strtoul(argv[++i], NULL, 16);
|
|
|
|
if (((i+1) < argc) && isdigit(argv[i+1][0]))
|
|
|
|
count = strtoul(argv[++i], NULL, 16);
|
|
|
|
mem_read(addr, count);
|
|
|
|
} else if (strcmp(argv[i], "mw") == 0) {
|
|
|
|
uint64_t addr, data;
|
|
|
|
|
|
|
|
if ((i+2) >= argc)
|
|
|
|
usage(argv[0]);
|
|
|
|
addr = strtoul(argv[++i], NULL, 16);
|
|
|
|
data = strtoul(argv[++i], NULL, 16);
|
|
|
|
mem_write(addr, data);
|
|
|
|
} else if (strcmp(argv[i], "load") == 0) {
|
|
|
|
const char *filename;
|
|
|
|
uint64_t addr = 0;
|
|
|
|
|
|
|
|
if ((i+1) >= argc)
|
|
|
|
usage(argv[0]);
|
|
|
|
filename = argv[++i];
|
|
|
|
if (((i+1) < argc) && isdigit(argv[i+1][0]))
|
|
|
|
addr = strtoul(argv[++i], NULL, 16);
|
|
|
|
load(filename, addr);
|
|
|
|
} else if (strcmp(argv[i], "gpr") == 0) {
|
|
|
|
uint64_t reg, count = 1;
|
|
|
|
|
|
|
|
if ((i+1) >= argc)
|
|
|
|
usage(argv[0]);
|
|
|
|
reg = strtoul(argv[++i], NULL, 10);
|
|
|
|
if (((i+1) < argc) && isdigit(argv[i+1][0]))
|
|
|
|
count = strtoul(argv[++i], NULL, 10);
|
|
|
|
gpr_read(reg, count);
|
|
|
|
} else {
|
|
|
|
fprintf(stderr, "Unknown command %s\n", argv[i]);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
core_status();
|
|
|
|
return 0;
|
|
|
|
}
|