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121 lines
2.6 KiB
VHDL
121 lines
2.6 KiB
VHDL
5 years ago
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity icache_tb is
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end icache_tb;
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architecture behave of icache_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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signal i_out : Fetch2ToIcacheType;
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signal i_in : IcacheToFetch2Type;
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signal wb_bram_in : wishbone_master_out;
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signal wb_bram_out : wishbone_slave_out;
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constant clk_period : time := 10 ns;
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begin
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icache0: entity work.icache
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generic map(
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LINE_SIZE_DW => 8,
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NUM_LINES => 4
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)
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port map(
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clk => clk,
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rst => rst,
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i_in => i_out,
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i_out => i_in,
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wishbone_out => wb_bram_in,
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wishbone_in => wb_bram_out
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);
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-- BRAM Memory slave
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bram0: entity work.mw_soc_memory
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generic map(
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MEMORY_SIZE => 128,
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RAM_INIT_FILE => "icache_test.bin"
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)
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port map(
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clk => clk,
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rst => rst,
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wishbone_in => wb_bram_in,
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wishbone_out => wb_bram_out
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 2*clk_period;
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rst <= '0';
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wait;
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end process;
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stim: process
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begin
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i_out.req <= '0';
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i_out.addr <= (others => '0');
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wait for 4*clk_period;
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i_out.req <= '1';
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i_out.addr <= x"0000000000000004";
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wait for 30*clk_period;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000001";
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i_out.req <= '0';
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wait for clk_period;
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-- hit
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i_out.req <= '1';
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i_out.addr <= x"0000000000000008";
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wait for clk_period/2;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000002";
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wait for clk_period/2;
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-- another miss
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i_out.req <= '1';
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i_out.addr <= x"0000000000000040";
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wait for 30*clk_period;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000010";
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-- test something that aliases
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i_out.req <= '1';
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i_out.addr <= x"0000000000000100";
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wait for clk_period/2;
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assert i_in.ack = '0';
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wait for clk_period/2;
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wait for 30*clk_period;
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assert i_in.ack = '1';
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assert i_in.insn = x"00000040";
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i_out.req <= '0';
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assert false report "end of test" severity failure;
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wait;
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end process;
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end;
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