microwatt/run.py

from pathlib import Path
from vunit import VUnit
from glob import glob

prj = VUnit.from_argv()
prj.add_osvvm()
root = Path(__file__).parent

lib = prj.add_library("lib")
lib.add_source_files(root / "litedram" / "extras" / "*.vhdl")
lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl")

# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
vhdl_files = glob(str(root / "*.vhdl"))
vhdl_files = [
    src_file
    for src_file in vhdl_files
    if ("xilinx-mult" not in src_file)
    and ("foreign_random" not in src_file)
    and ("nonrandom" not in src_file)
]
lib.add_source_files(vhdl_files)

unisim = prj.add_library("unisim")
unisim.add_source_files(root / "sim-unisim" / "*.vhdl")

prj.set_sim_option("disable_ieee_warnings", True)

prj.main()
Added VUnit run script. The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies. The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project. At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago			`from pathlib import Path`
			`from vunit import VUnit`
			`from glob import glob`

			`prj = VUnit.from_argv()`
Make core testbenches recognized by VUnit This commit also removes the dependencies these testbenches have on VHPIDIRECT. The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists. For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions. The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using the -p option to the run.py script Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago			`prj.add_osvvm()`
Added VUnit run script. The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies. The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project. At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago			`root = Path(__file__).parent`

			`lib = prj.add_library("lib")`
Replaced VHDL assert and report with VUnit checking and logging The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging. These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve - Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected. VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you. - The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures. info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used. Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to extend the standard CLI of VUnit to add new options and you can also set generics from the run script. - VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages. Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs. - Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent option allowing you to suppress those messages. That option has been enabled. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago			`lib.add_source_files(root / "litedram" / "extras" / "*.vhdl")`
			`lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl")`
Added VUnit run script. The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies. The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project. At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago
Make core testbenches recognized by VUnit This commit also removes the dependencies these testbenches have on VHPIDIRECT. The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists. For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions. The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using the -p option to the run.py script Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago			`# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.`
			`vhdl_files = glob(str(root / "*.vhdl"))`
			`vhdl_files = [`
			`src_file`
			`for src_file in vhdl_files`
			`if ("xilinx-mult" not in src_file)`
			`and ("foreign_random" not in src_file)`
			`and ("nonrandom" not in src_file)`
			`]`
			`lib.add_source_files(vhdl_files)`
Added VUnit run script. The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies. The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project. At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago
			`unisim = prj.add_library("unisim")`
Replaced VHDL assert and report with VUnit checking and logging The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging. These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve - Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected. VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you. - The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures. info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used. Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to extend the standard CLI of VUnit to add new options and you can also set generics from the run script. - VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages. Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs. - Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent option allowing you to suppress those messages. That option has been enabled. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago			`unisim.add_source_files(root / "sim-unisim" / "*.vhdl")`

			`prj.set_sim_option("disable_ieee_warnings", True)`
Added VUnit run script. The VUnit run script will find all VHDL files based on given search patterns, figure out their dependencies, and support incremental compile based on the dependencies. The same script is used for all VUnit supported simulators. Supporting several simulators simplifies the adoption of this project. At this point only compilation is performed. Coming commits will enable simulation of VHDL testbenches. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com> 4 years ago
			`prj.main()`