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@ -199,9 +199,14 @@ architecture behave of loadstore1 is
@@ -199,9 +199,14 @@ architecture behave of loadstore1 is
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return std_ulogic_vector is |
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variable longsel : std_ulogic_vector(15 downto 0); |
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begin |
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longsel := "00000000" & length_to_sel(size); |
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return std_ulogic_vector(shift_left(unsigned(longsel), |
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to_integer(unsigned(address)))); |
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if is_X(address) then |
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longsel := (others => 'X'); |
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return longsel; |
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else |
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longsel := "00000000" & length_to_sel(size); |
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return std_ulogic_vector(shift_left(unsigned(longsel), |
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to_integer(unsigned(address)))); |
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end if; |
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end function xfer_data_sel; |
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-- 23-bit right shifter for DP -> SP float conversions |
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@ -401,7 +406,7 @@ begin
@@ -401,7 +406,7 @@ begin
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variable addr_mask : std_ulogic_vector(2 downto 0); |
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begin |
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v := request_init; |
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sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10)); |
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sprn := l_in.insn(15 downto 11) & l_in.insn(20 downto 16); |
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v.valid := l_in.valid; |
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v.instr_tag := l_in.instr_tag; |
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