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@ -239,12 +239,20 @@ architecture behaviour of soc is
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SLAVE_IO_ICP,
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SLAVE_IO_ICS,
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SLAVE_IO_UART1,
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SLAVE_IO_SPI_FLASH_REG,
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SLAVE_IO_SPI_FLASH_MAP,
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SLAVE_IO_SPI_FLASH,
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SLAVE_IO_GPIO,
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SLAVE_IO_EXTERNAL,
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SLAVE_IO_NONE);
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signal slave_io_dbg : slave_io_type;
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SLAVE_IO_EXTERNAL);
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signal current_io_decode : slave_io_type;
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signal io_cycle_none : std_ulogic;
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signal io_cycle_syscon : std_ulogic;
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signal io_cycle_uart : std_ulogic;
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signal io_cycle_uart1 : std_ulogic;
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signal io_cycle_icp : std_ulogic;
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signal io_cycle_ics : std_ulogic;
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signal io_cycle_spi_flash : std_ulogic;
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signal io_cycle_gpio : std_ulogic;
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signal io_cycle_external : std_ulogic;
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function wishbone_widen_data(wb : wb_io_master_out) return wishbone_master_out is
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variable wwb : wishbone_master_out;
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@ -465,14 +473,20 @@ begin
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-- Misc
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variable has_top : boolean;
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variable has_bot : boolean;
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variable do_cyc : std_ulogic;
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variable end_cyc : std_ulogic;
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variable slave_io : slave_io_type;
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variable match : std_ulogic_vector(31 downto 12);
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begin
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if rising_edge(system_clk) then
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do_cyc := '0';
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end_cyc := '0';
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if (rst) then
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state := IDLE;
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wb_io_out.ack <= '0';
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wb_io_out.stall <= '0';
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wb_sio_out.cyc <= '0';
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wb_sio_out.stb <= '0';
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end_cyc := '1';
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has_top := false;
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has_bot := false;
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else
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@ -488,7 +502,7 @@ begin
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wb_io_out.stall <= '1';
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-- Start cycle downstream
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wb_sio_out.cyc <= '1';
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do_cyc := '1';
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wb_sio_out.stb <= '1';
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-- Copy write enable to IO out, copy address as well
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@ -551,8 +565,8 @@ begin
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-- Wait for new ack
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state := WAIT_ACK_TOP;
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else
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-- We are done, ack up, clear cyc downstram
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wb_sio_out.cyc <= '0';
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-- We are done, ack up, clear cyc downstream
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end_cyc := '1';
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-- And ack & unstall upstream
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wb_io_out.ack <= '1';
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@ -576,7 +590,7 @@ begin
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end if;
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-- We are done, ack up, clear cyc downstram
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wb_sio_out.cyc <= '0';
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end_cyc := '1';
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-- And ack & unstall upstream
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wb_io_out.ack <= '1';
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@ -587,144 +601,149 @@ begin
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end if;
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end case;
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end if;
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-- Create individual registered cycle signals for the wishbones
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-- going to the various peripherals
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if do_cyc = '1' or end_cyc = '1' then
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io_cycle_none <= '0';
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io_cycle_syscon <= '0';
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io_cycle_uart <= '0';
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io_cycle_uart1 <= '0';
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io_cycle_icp <= '0';
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io_cycle_ics <= '0';
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io_cycle_spi_flash <= '0';
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io_cycle_gpio <= '0';
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io_cycle_external <= '0';
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wb_sio_out.cyc <= '0';
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wb_ext_is_dram_init <= '0';
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wb_spiflash_is_map <= '0';
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wb_spiflash_is_reg <= '0';
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wb_ext_is_dram_csr <= '0';
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wb_ext_is_eth <= '0';
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wb_ext_is_sdcard <= '0';
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end if;
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if do_cyc = '1' then
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-- Decode I/O address
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-- This is real address bits 29 downto 12
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match := "11" & wb_io_in.adr(26 downto 9);
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slave_io := SLAVE_IO_SYSCON;
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if std_match(match, x"FF---") and HAS_DRAM then
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slave_io := SLAVE_IO_EXTERNAL;
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io_cycle_external <= '1';
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wb_ext_is_dram_init <= '1';
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elsif std_match(match, x"F----") then
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slave_io := SLAVE_IO_SPI_FLASH;
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io_cycle_spi_flash <= '1';
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wb_spiflash_is_map <= '1';
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elsif std_match(match, x"C8---") then
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-- Ext IO "chip selects"
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if std_match(match, x"--00-") and HAS_DRAM then
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slave_io := SLAVE_IO_EXTERNAL;
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io_cycle_external <= '1';
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wb_ext_is_dram_csr <= '1';
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elsif (std_match(match, x"--02-") or std_match(match, x"--03-")) and
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HAS_LITEETH then
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slave_io := SLAVE_IO_EXTERNAL;
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io_cycle_external <= '1';
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wb_ext_is_eth <= '1';
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elsif std_match(match, x"--04-") and HAS_SD_CARD then
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slave_io := SLAVE_IO_EXTERNAL;
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io_cycle_external <= '1';
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wb_ext_is_sdcard <= '1';
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else
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io_cycle_none <= '1';
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end if;
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elsif std_match(match, x"C0000") then
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slave_io := SLAVE_IO_SYSCON;
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io_cycle_syscon <= '1';
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elsif std_match(match, x"C0002") then
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slave_io := SLAVE_IO_UART;
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io_cycle_uart <= '1';
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elsif std_match(match, x"C0003") then
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slave_io := SLAVE_IO_UART1;
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io_cycle_uart1 <= '1';
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elsif std_match(match, x"C0004") then
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slave_io := SLAVE_IO_ICP;
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io_cycle_icp <= '1';
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elsif std_match(match, x"C0005") then
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slave_io := SLAVE_IO_ICS;
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io_cycle_ics <= '1';
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elsif std_match(match, x"C0006") then
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slave_io := SLAVE_IO_SPI_FLASH;
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io_cycle_spi_flash <= '1';
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wb_spiflash_is_reg <= '1';
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elsif std_match(match, x"C0007") then
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slave_io := SLAVE_IO_GPIO;
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io_cycle_gpio <= '1';
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else
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io_cycle_none <= '1';
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end if;
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current_io_decode <= slave_io;
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wb_sio_out.cyc <= '1';
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end if;
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end if;
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end process;
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-- IO wishbone slave intercon.
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-- IO wishbone slave interconnect.
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--
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slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
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wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
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wb_spiflash_out)
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variable slave_io : slave_io_type;
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variable match : std_ulogic_vector(31 downto 12);
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variable ext_valid : boolean;
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slave_io_intercon: process(all)
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begin
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-- Simple address decoder.
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slave_io := SLAVE_IO_NONE;
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match := "11" & wb_sio_out.adr(27 downto 10);
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if std_match(match, x"FF---") and HAS_DRAM then
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slave_io := SLAVE_IO_EXTERNAL;
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elsif std_match(match, x"F----") then
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slave_io := SLAVE_IO_SPI_FLASH_MAP;
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elsif std_match(match, x"C0000") then
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slave_io := SLAVE_IO_SYSCON;
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elsif std_match(match, x"C0002") then
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slave_io := SLAVE_IO_UART;
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elsif std_match(match, x"C0003") then
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slave_io := SLAVE_IO_UART1;
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elsif std_match(match, x"C8---") then
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slave_io := SLAVE_IO_EXTERNAL;
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elsif std_match(match, x"C0004") then
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slave_io := SLAVE_IO_ICP;
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elsif std_match(match, x"C0005") then
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slave_io := SLAVE_IO_ICS;
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elsif std_match(match, x"C0006") then
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slave_io := SLAVE_IO_SPI_FLASH_REG;
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elsif std_match(match, x"C0007") then
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slave_io := SLAVE_IO_GPIO;
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end if;
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slave_io_dbg <= slave_io;
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wb_uart0_in <= wb_sio_out;
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wb_uart0_in.cyc <= '0';
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wb_uart0_in.cyc <= io_cycle_uart;
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wb_uart1_in <= wb_sio_out;
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wb_uart1_in.cyc <= '0';
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wb_uart1_in.cyc <= io_cycle_uart1;
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wb_spiflash_in <= wb_sio_out;
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wb_spiflash_in.cyc <= '0';
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wb_spiflash_is_reg <= '0';
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wb_spiflash_is_map <= '0';
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wb_spiflash_in.cyc <= io_cycle_spi_flash;
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-- Clear top bits so they don't make their way to the
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-- flash chip.
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wb_spiflash_in.adr(27 downto 26) <= "00";
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wb_gpio_in <= wb_sio_out;
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wb_gpio_in.cyc <= '0';
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wb_gpio_in.cyc <= io_cycle_gpio;
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-- Only give xics 8 bits of wb addr (for now...)
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wb_xics_icp_in <= wb_sio_out;
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wb_xics_icp_in.adr <= (others => '0');
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wb_xics_icp_in.adr(5 downto 0) <= wb_sio_out.adr(5 downto 0);
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wb_xics_icp_in.cyc <= '0';
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wb_xics_icp_in.cyc <= io_cycle_icp;
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wb_xics_ics_in <= wb_sio_out;
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wb_xics_ics_in.adr <= (others => '0');
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wb_xics_ics_in.adr(9 downto 0) <= wb_sio_out.adr(9 downto 0);
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wb_xics_ics_in.cyc <= '0';
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wb_xics_ics_in.cyc <= io_cycle_ics;
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wb_ext_io_in <= wb_sio_out;
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wb_ext_io_in.cyc <= '0';
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wb_ext_io_in.cyc <= io_cycle_external;
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wb_syscon_in <= wb_sio_out;
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wb_syscon_in.cyc <= '0';
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wb_ext_is_dram_csr <= '0';
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wb_ext_is_dram_init <= '0';
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wb_ext_is_eth <= '0';
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wb_ext_is_sdcard <= '0';
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wb_syscon_in.cyc <= io_cycle_syscon;
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-- Default response, ack & return all 1's
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wb_sio_in.dat <= (others => '1');
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wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
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wb_sio_in.stall <= '0';
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case slave_io is
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case current_io_decode is
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when SLAVE_IO_EXTERNAL =>
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-- Ext IO "chip selects"
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--
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-- DRAM init is special at 0xFF* so we just test the top
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-- bit. Everything else is at 0xC8* so we test only bits
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-- 23 downto 16 (21 downto 14 in the wishbone addr).
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--
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ext_valid := false;
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if wb_sio_out.adr(27) = '1' and HAS_DRAM then -- DRAM init is special
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wb_ext_is_dram_init <= '1';
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ext_valid := true;
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elsif wb_sio_out.adr(21 downto 14) = x"00" and HAS_DRAM then
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wb_ext_is_dram_csr <= '1';
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ext_valid := true;
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elsif wb_sio_out.adr(21 downto 14) = x"02" and HAS_LITEETH then
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wb_ext_is_eth <= '1';
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ext_valid := true;
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elsif wb_sio_out.adr(21 downto 14) = x"03" and HAS_LITEETH then
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wb_ext_is_eth <= '1';
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ext_valid := true;
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elsif wb_sio_out.adr(21 downto 14) = x"04" and HAS_SD_CARD then
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wb_ext_is_sdcard <= '1';
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ext_valid := true;
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end if;
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if ext_valid then
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wb_ext_io_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_ext_io_out;
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end if;
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wb_sio_in <= wb_ext_io_out;
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when SLAVE_IO_SYSCON =>
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wb_syscon_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_syscon_out;
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when SLAVE_IO_UART =>
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wb_uart0_in.cyc <= wb_sio_out.cyc;
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wb_sio_in <= wb_uart0_out;
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when SLAVE_IO_ICP =>
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|
|
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wb_xics_icp_in.cyc <= wb_sio_out.cyc;
|
|
|
|
|
wb_sio_in <= wb_xics_icp_out;
|
|
|
|
|
when SLAVE_IO_ICS =>
|
|
|
|
|
wb_xics_ics_in.cyc <= wb_sio_out.cyc;
|
|
|
|
|
wb_sio_in <= wb_xics_ics_out;
|
|
|
|
|
when SLAVE_IO_UART1 =>
|
|
|
|
|
wb_uart1_in.cyc <= wb_sio_out.cyc;
|
|
|
|
|
wb_sio_in <= wb_uart1_out;
|
|
|
|
|
when SLAVE_IO_SPI_FLASH_MAP =>
|
|
|
|
|
-- Clear top bits so they don't make their way to the
|
|
|
|
|
-- fash chip.
|
|
|
|
|
wb_spiflash_in.adr(27 downto 26) <= "00";
|
|
|
|
|
wb_spiflash_in.cyc <= wb_sio_out.cyc;
|
|
|
|
|
when SLAVE_IO_SPI_FLASH =>
|
|
|
|
|
wb_sio_in <= wb_spiflash_out;
|
|
|
|
|
wb_spiflash_is_map <= '1';
|
|
|
|
|
when SLAVE_IO_SPI_FLASH_REG =>
|
|
|
|
|
wb_spiflash_in.cyc <= wb_sio_out.cyc;
|
|
|
|
|
wb_sio_in <= wb_spiflash_out;
|
|
|
|
|
wb_spiflash_is_reg <= '1';
|
|
|
|
|
when SLAVE_IO_GPIO =>
|
|
|
|
|
wb_gpio_in.cyc <= wb_sio_out.cyc;
|
|
|
|
|
wb_sio_in <= wb_gpio_out;
|
|
|
|
|
when others =>
|
|
|
|
|
end case;
|
|
|
|
|
|
|
|
|
|
-- Default response, ack & return all 1's
|
|
|
|
|
if io_cycle_none = '1' then
|
|
|
|
|
wb_sio_in.dat <= (others => '1');
|
|
|
|
|
wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
|
|
|
|
|
wb_sio_in.stall <= '0';
|
|
|
|
|
end if;
|
|
|
|
|
|
|
|
|
|
end process;
|
|
|
|
|
|
|
|
|
|
-- Syscon slave
|
|
|
|
|