ECPIX-5: Add litedram support
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>pull/428/head
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# Based on orangecrab-85-0.2.yml and arty.yml
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{
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"cpu": "None", # CPU type (ex vexriscv, serv, None)
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"device": "LFE5UM5G-85F-8BG554I",
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"memtype": "DDR3", # DRAM type
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"cmd_latency": 0,
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"sdram_module": "MT41K256M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 2, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
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# Electrical ---------------------------------------------------------------
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"rtt_nom": "60ohm", # Nominal termination. (Default)
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"rtt_wr": "60ohm", # Write termination. (Default)
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"ron": "34ohm", # Output driver impedance. (Default)
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 100e6, # Input clock frequency
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"sys_clk_freq": 50e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"init_clk_freq": 50e6, # ?
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"native_0": {
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"type": "native",
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"block_until_ready": False,
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},
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},
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}
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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use work.utils.all;
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entity dram_init_mem is
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generic (
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EXTRA_PAYLOAD_FILE : string := "";
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EXTRA_PAYLOAD_SIZE : integer := 0
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);
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port (
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clk : in std_ulogic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out
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);
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end entity dram_init_mem;
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architecture rtl of dram_init_mem is
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constant INIT_RAM_SIZE : integer := 24576;
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constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
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constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
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constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
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constant INIT_RAM_FILE : string := "litedram_core.init";
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type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
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-- XXX FIXME: Have a single init function called twice with
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-- an offset as argument
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procedure init_load_payload(ram: inout ram_t; filename: string) is
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file payload_file : text open read_mode is filename;
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variable ram_line : line;
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variable temp_word : std_logic_vector(63 downto 0);
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begin
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for i in 0 to RND_PAYLOAD_SIZE-1 loop
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exit when endfile(payload_file);
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readline(payload_file, ram_line);
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hread(ram_line, temp_word);
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ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
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ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
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end loop;
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assert endfile(payload_file) report "Payload too big !" severity failure;
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end procedure;
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impure function init_load_ram(name : string) return ram_t is
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file ram_file : text open read_mode is name;
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variable temp_word : std_logic_vector(63 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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variable ram_line : line;
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begin
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report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
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" rounded to:" & integer'image(RND_PAYLOAD_SIZE);
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report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
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" bytes using " & integer'image(INIT_RAM_ABITS) &
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" address bits";
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for i in 0 to (INIT_RAM_SIZE/8)-1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i*2) := temp_word(31 downto 0);
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temp_ram(i*2+1) := temp_word(63 downto 32);
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end loop;
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if RND_PAYLOAD_SIZE /= 0 then
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init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
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end if;
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return temp_ram;
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end function;
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impure function init_zero return ram_t is
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variable temp_ram : ram_t := (others => (others => '0'));
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begin
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return temp_ram;
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end function;
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impure function initialize_ram(filename: string) return ram_t is
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begin
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report "Opening file " & filename;
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if filename'length = 0 then
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return init_zero;
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else
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return init_load_ram(filename);
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end if;
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end function;
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signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
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attribute ram_style : string;
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attribute ram_style of init_ram: signal is "block";
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signal obuf : std_ulogic_vector(31 downto 0);
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signal oack : std_ulogic;
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begin
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init_ram_0: process(clk)
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variable adr : integer;
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begin
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if rising_edge(clk) then
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oack <= '0';
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if (wb_in.cyc and wb_in.stb) = '1' then
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adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
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if wb_in.we = '0' then
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obuf <= init_ram(adr);
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else
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for i in 0 to 3 loop
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if wb_in.sel(i) = '1' then
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init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
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wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
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end if;
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end loop;
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end if;
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oack <= '1';
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end if;
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wb_out.ack <= oack;
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wb_out.dat <= obuf;
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end if;
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end process;
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wb_out.stall <= '0';
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end architecture rtl;
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