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@ -39,7 +39,7 @@ sim_provides = {
@@ -39,7 +39,7 @@ sim_provides = {
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"dmi_dtm" : "dmi_dtm_xilinx.vhdl", |
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"clock_generator" : "fpga/clk_gen_bypass.vhd", |
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"main_bram" : "sim_bram.vhdl", |
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"pp_soc_uart" : "sim_uart.vhdl" |
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"pp_soc_uart" : "sim_pp_uart.vhdl" |
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} |
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if synth: |
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