Browse Source

uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/213/head
Benjamin Herrenschmidt 3 years ago
parent
commit
4eae29801b
  1. 2
      Makefile
  2. 2
      scripts/dependencies.py
  3. 0
      sim_pp_uart.vhdl

2
Makefile

@ -55,7 +55,7 @@ soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_ @@ -55,7 +55,7 @@ soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_
spi_rxtx.vhdl spi_flash_ctrl.vhdl


soc_sim_files = $(soc_files) sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl

soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \

2
scripts/dependencies.py

@ -39,7 +39,7 @@ sim_provides = { @@ -39,7 +39,7 @@ sim_provides = {
"dmi_dtm" : "dmi_dtm_xilinx.vhdl",
"clock_generator" : "fpga/clk_gen_bypass.vhd",
"main_bram" : "sim_bram.vhdl",
"pp_soc_uart" : "sim_uart.vhdl"
"pp_soc_uart" : "sim_pp_uart.vhdl"
}

if synth:

0
sim_uart.vhdl → sim_pp_uart.vhdl

Loading…
Cancel
Save