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@ -173,6 +173,7 @@ begin
@@ -173,6 +173,7 @@ begin
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terminated <= '0'; |
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log_trigger_delay <= 0; |
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gspr_index <= (others => '0'); |
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log_dmi_addr <= (others => '0'); |
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else |
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if do_log_trigger = '1' or log_trigger_delay /= 0 then |
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if log_trigger_delay = 255 or |
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@ -334,6 +335,7 @@ begin
@@ -334,6 +335,7 @@ begin
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addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is |
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variable firstbit : integer; |
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begin |
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assert not is_X(addr); |
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firstbit := to_integer(unsigned(addr(1 downto 0))) * 64; |
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return data(firstbit + 63 downto firstbit); |
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end; |
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@ -351,9 +353,14 @@ begin
@@ -351,9 +353,14 @@ begin
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begin |
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if rising_edge(clk) then |
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if log_wr_enable = '1' then |
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assert not is_X(log_wr_ptr); |
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log_array(to_integer(log_wr_ptr)) <= log_data; |
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end if; |
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log_rd <= log_array(to_integer(log_rd_ptr_latched)); |
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if is_X(log_rd_ptr_latched) then |
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log_rd <= (others => 'X'); |
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else |
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log_rd <= log_array(to_integer(log_rd_ptr_latched)); |
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end if; |
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end if; |
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end process; |
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@ -366,6 +373,7 @@ begin
@@ -366,6 +373,7 @@ begin
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if rst = '1' then |
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log_wr_ptr <= (others => '0'); |
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log_toggle <= '0'; |
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log_rd_ptr_latched <= (others => '0'); |
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elsif log_wr_enable = '1' then |
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if log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS) then |
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log_toggle <= not log_toggle; |
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