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This reworks (and simplifies) plru_tb to use the new plrufn module instead of the old (and now unused) plru module. The latter is now removed completely. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/414/head

4 changed files with 60 additions and 159 deletions
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@@ -1,86 +0,0 @@
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use ieee.math_real.all; |
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entity plru is |
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generic ( |
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BITS : positive := 2 |
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) |
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; |
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port ( |
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clk : in std_ulogic; |
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rst : in std_ulogic; |
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acc : in std_ulogic_vector(BITS-1 downto 0); |
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acc_en : in std_ulogic; |
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lru : out std_ulogic_vector(BITS-1 downto 0) |
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); |
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end entity plru; |
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architecture rtl of plru is |
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-- Each level of the tree (from leaf to root) has half the number of nodes |
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-- of the previous level. So for a 2^N bits LRU, we have a level of N/2 bits |
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-- one of N/4 bits etc.. down to 1. This gives us 2^N-1 nodes. Ie, 2 bits |
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-- LRU has 3 nodes (2 + 1), 4 bits LRU has 15 nodes (8 + 4 + 2 + 1) etc... |
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constant count : positive := 2 ** BITS - 1; |
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subtype node_t is integer range 0 to count - 1; |
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type tree_t is array(node_t) of std_ulogic; |
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signal tree: tree_t; |
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begin |
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-- XXX Check if we can turn that into a little ROM instead that |
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-- takes the tree bit vector and returns the LRU. See if it's better |
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-- in term of FPGA resource usage... |
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get_lru: process(tree) |
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variable node : node_t; |
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variable abit : std_ulogic; |
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begin |
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node := 0; |
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for i in 0 to BITS-1 loop |
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-- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node)); |
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abit := tree(node); |
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lru(BITS-1-i) <= abit; |
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if i /= BITS-1 then |
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node := node * 2; |
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if abit = '1' then |
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node := node + 2; |
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else |
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node := node + 1; |
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end if; |
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end if; |
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end loop; |
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end process; |
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update_lru: process(clk) |
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variable node : node_t; |
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variable abit : std_ulogic; |
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begin |
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if rising_edge(clk) then |
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if rst = '1' then |
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tree <= (others => '0'); |
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elsif acc_en = '1' then |
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node := 0; |
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for i in 0 to BITS-1 loop |
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abit := acc(BITS-1-i); |
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tree(node) <= not abit; |
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-- report "UPD: i:" & integer'image(i) & " node:" & integer'image(node) & " val" & std_ulogic'image(not abit); |
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if i /= BITS-1 then |
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node := node * 2; |
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if abit = '1' then |
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node := node + 2; |
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else |
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node := node + 1; |
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end if; |
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end if; |
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end loop; |
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end if; |
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end if; |
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-- if falling_edge(clk) then |
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-- if acc_en = '1' then |
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-- report "UPD: tree:" & to_string(tree); |
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-- end if; |
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-- end if; |
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end process; |
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end; |
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